MT Architecture Documentation
DISCLAIMER: This documentation is derived from the cgen cpu description
of this architecture, and does not represent official documentation
of the chip maker.
In cgen-parlance, an architecture consists of machines and models.
A `machine' is the specification of a variant of the architecture,
and a `model' is the implementation of that specification.
Typically there is a one-to-one correspondance between machine and model.
The distinction allows for separation of what application programs see
(the machine), and how to tune for the chip (what the compiler sees).
A "cpu family" is a cgen concoction to help organize the generated code.
Chip variants that are quite dissimilar can be treated separately by the
generated code even though they're both members of the same architecture.
MT Architecture
This section describes various things about the cgen description of
the MT architecture. Familiarity with cgen cpu descriptions
is assumed.
Bit number orientation (arch.lsb0?): lsb = 0
ISA description
-
mt - Morpho Technologies MT ISA
- default-insn-word-bitsize: 32
- default-insn-bitsize: 32
- base-insn-bitsize: 32
- decode-assist:
- decode-splits:
- parallel-insns: 2
CPU Families
-
ms1-003bf - Morpho Technologies mRISC family
Machines:
-
ms1-003 - Morpho Technologies mrisc
Models:
-
ms1-003 - Morpho Technologies mrisc
-
ms1bf - Morpho Technologies mRISC family
Machines:
-
ms1 - Morpho Technologies mrisc
Models:
-
ms1 - Morpho Technologies mrisc
-
ms2bf - Morpho Technologies mRISC family
Machines:
-
ms2 - Morpho Technologies ms2
Models:
-
ms2 - Morpho Technologies ms2
Machine variants
ms1 - Morpho Technologies mrisc
ms1-003 - Morpho Technologies mrisc
-
bfd-name: ms1-003
-
isas: mt
ms2 - Morpho Technologies ms2
Model variants
ms1 - Morpho Technologies mrisc
ms1-003 - Morpho Technologies mrisc
ms2 - Morpho Technologies ms2
Registers
h-pc - program counter
-
machines: base
-
bitsize: 32
h-spr - special-purpose registers
-
machines: base
-
bitsize: 32
-
array: [16]
names:
R0 |
0 |
R1 |
1 |
R2 |
2 |
R3 |
3 |
R4 |
4 |
R5 |
5 |
R6 |
6 |
R7 |
7 |
R8 |
8 |
R9 |
9 |
R10 |
10 |
R11 |
11 |
R12 |
12 |
fp |
12 |
R13 |
13 |
sp |
13 |
R14 |
14 |
ra |
14 |
R15 |
15 |
ira |
15 |
Assembler supplemental
This documentation was machine generated from the cgen cpu description
files for this architecture.
http://sources.redhat.com/cgen/