LM32 Architecture Documentation
DISCLAIMER: This documentation is derived from the cgen cpu description
of this architecture, and does not represent official documentation
of the chip maker.
In cgen-parlance, an architecture consists of machines and models.
A `machine' is the specification of a variant of the architecture,
and a `model' is the implementation of that specification.
Typically there is a one-to-one correspondance between machine and model.
The distinction allows for separation of what application programs see
(the machine), and how to tune for the chip (what the compiler sees).
A "cpu family" is a cgen concoction to help organize the generated code.
Chip variants that are quite dissimilar can be treated separately by the
generated code even though they're both members of the same architecture.
LM32 Architecture
This section describes various things about the cgen description of
the LM32 architecture. Familiarity with cgen cpu descriptions
is assumed.
Bit number orientation (arch.lsb0?): lsb = 0
ISA description
-
lm32 - Lattice Mico32 ISA
- default-insn-word-bitsize: 32
- default-insn-bitsize: 32
- base-insn-bitsize: 32
- decode-assist: 31 30 29 28 27 26
- decode-splits:
CPU Families
-
lm32bf - Lattice Mico32 CPU
Machines:
-
lm32 - Lattice Mico32 MACH
Models:
-
lm32 - Lattice Mico32 reference implementation
Machine variants
lm32 - Lattice Mico32 MACH
-
bfd-name: lm32
-
isas: lm32
Model variants
lm32 - Lattice Mico32 reference implementation
Registers
h-csr - Control and status registers
-
machines: base
-
bitsize: 32
-
array: [32]
names:
IE |
0 |
IM |
1 |
IP |
2 |
ICC |
3 |
DCC |
4 |
CC |
5 |
CFG |
6 |
EBA |
7 |
DC |
8 |
DEBA |
9 |
JTX |
14 |
JRX |
15 |
BP0 |
16 |
BP1 |
17 |
BP2 |
18 |
BP3 |
19 |
WP0 |
24 |
WP1 |
25 |
WP2 |
26 |
WP3 |
27 |
h-gr - General purpose registers
-
machines: base
-
bitsize: 32
-
array: [32]
names:
gp |
26 |
fp |
27 |
sp |
28 |
ra |
29 |
ea |
30 |
ba |
31 |
r0 |
0 |
r1 |
1 |
r2 |
2 |
r3 |
3 |
r4 |
4 |
r5 |
5 |
r6 |
6 |
r7 |
7 |
r8 |
8 |
r9 |
9 |
r10 |
10 |
r11 |
11 |
r12 |
12 |
r13 |
13 |
r14 |
14 |
r15 |
15 |
r16 |
16 |
r17 |
17 |
r18 |
18 |
r19 |
19 |
r20 |
20 |
r21 |
21 |
r22 |
22 |
r23 |
23 |
r24 |
24 |
r25 |
25 |
r26 |
26 |
r27 |
27 |
r28 |
28 |
r29 |
29 |
r30 |
30 |
r31 |
31 |
h-pc - Program counter
-
machines: base
-
bitsize: 32
Assembler supplemental
This documentation was machine generated from the cgen cpu description
files for this architecture.
http://sources.redhat.com/cgen/