FR30 Instruction Documentation

Instructions

Instructions for each machine:

fr30 - Generic FR30 cpu

MEM - Memory
ALU - ALU
BR - Branch
alphabetically

Individual instructions descriptions

add - add reg/reg

machines: base

syntax: add $Rj,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0xa 0x6 Rj Ri

semantics:

(sequence
  ()
  (set vbit (add-oflag Ri Rj 0))
  (set cbit (add-cflag Ri Rj 0))
  (set Ri (add Ri Rj))
  (sequence
    ()
    (set zbit (eq Ri 0))
    (set nbit (lt Ri 0))))

add2 - add2 immed/reg

machines: base

syntax: add2 $m4,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-m4 f-Ri

0xa 0x5 m4 Ri

semantics:

(sequence
  ()
  (set vbit (add-oflag Ri m4 0))
  (set cbit (add-cflag Ri m4 0))
  (set Ri (add Ri m4))
  (sequence
    ()
    (set zbit (eq Ri 0))
    (set nbit (lt Ri 0))))

addc - addc reg/reg

machines: base

syntax: addc $Rj,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0xa 0x7 Rj Ri

semantics:

(sequence
  ((WI tmp))
  (set tmp (addc Ri Rj cbit))
  (set vbit (add-oflag Ri Rj cbit))
  (set cbit (add-cflag Ri Rj cbit))
  (set Ri tmp)
  (sequence
    ()
    (set zbit (eq Ri 0))
    (set nbit (lt Ri 0))))

addi - add immed/reg

machines: base

syntax: add $u4,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-u4 f-Ri

0xa 0x4 u4 Ri

semantics:

(sequence
  ()
  (set vbit (add-oflag Ri u4 0))
  (set cbit (add-cflag Ri u4 0))
  (set Ri (add Ri u4))
  (sequence
    ()
    (set zbit (eq Ri 0))
    (set nbit (lt Ri 0))))

addn - addn reg/reg

machines: base

syntax: addn $Rj,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0xa 0x2 Rj Ri

semantics:
```
(set Ri (add Ri Rj))
```

addn2 - addn2 immed/reg

machines: base

syntax: addn2 $m4,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-m4 f-Ri

0xa 0x1 m4 Ri

semantics:
```
(set Ri (add Ri m4))
```

addni - addn immed/reg

machines: base

syntax: addn $u4,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-u4 f-Ri

0xa 0x0 u4 Ri

semantics:
```
(set Ri (add Ri u4))
```

addsp - addsp #s10

machines: base

syntax: addsp $s10

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-s10

0xa 0x3 s10

semantics:

(set (reg h-gr 15) (add (reg h-gr 15) s10))

and - and reg/reg

machines: base

syntax: and $Rj,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x8 0x2 Rj Ri

semantics:

(sequence
  ()
  (set Ri (and Ri Rj))
  (sequence
    ()
    (set zbit (eq Ri 0))
    (set nbit (lt Ri 0))))

andb - andb reg/mem

machines: base

syntax: andb $Rj,@$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x8 0x6 Rj Ri

semantics:

(sequence
  ((QI tmp))
  (set QI tmp (and QI (mem QI Ri) Rj))
  (sequence
    ()
    (set zbit (eq tmp 0))
    (set nbit (lt tmp 0)))
  (set QI (mem QI Ri) tmp))

execution unit(s):
- fr30-1: u-exec u-load u-store

andccr - andccr #u8

machines: base

syntax: andccr $u8

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-u8

0x8 0x3 u8

semantics:
```
(set ccr (and ccr u8))
```

andh - andh reg/mem

machines: base

syntax: andh $Rj,@$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x8 0x5 Rj Ri

semantics:

(sequence
  ((HI tmp))
  (set HI tmp (and HI (mem HI Ri) Rj))
  (sequence
    ()
    (set zbit (eq tmp 0))
    (set nbit (lt tmp 0)))
  (set HI (mem HI Ri) tmp))

execution unit(s):
- fr30-1: u-exec u-load u-store

andm - and reg/mem

machines: base

syntax: and $Rj,@$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x8 0x4 Rj Ri

semantics:

(sequence
  ((WI tmp))
  (set WI tmp (and WI (mem WI Ri) Rj))
  (sequence
    ()
    (set zbit (eq tmp 0))
    (set nbit (lt tmp 0)))
  (set WI (mem WI Ri) tmp))

execution unit(s):
- fr30-1: u-exec u-load u-store

asr - asr Rj,Ri

machines: base

syntax: asr $Rj,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0xb 0xa Rj Ri

semantics:

(sequence
  ((WI shift))
  (set shift (and Rj 31))
  (if (ne shift 0)
      (sequence
        ()
        (set cbit (ne (and Ri (sll 1 (sub shift 1))) 0))
        (set Ri (sra Ri shift)))
      (set cbit 0))
  (set nbit (lt Ri 0))
  (set zbit (eq Ri 0)))

asr2 - asr2 u4,Ri

machines: base

syntax: asr2 $u4,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-u4 f-Ri

0xb 0x9 u4 Ri

semantics:

(sequence
  ((WI shift))
  (set shift (add u4 16))
  (if (ne shift 0)
      (sequence
        ()
        (set cbit (ne (and Ri (sll 1 (sub shift 1))) 0))
        (set Ri (sra Ri shift)))
      (set cbit 0))
  (set nbit (lt Ri 0))
  (set zbit (eq Ri 0)))

asri - asr u4,Ri

machines: base

syntax: asr $u4,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-u4 f-Ri

0xb 0x8 u4 Ri

semantics:

(sequence
  ((WI shift))
  (set shift u4)
  (if (ne shift 0)
      (sequence
        ()
        (set cbit (ne (and Ri (sll 1 (sub shift 1))) 0))
        (set Ri (sra Ri shift)))
      (set cbit 0))
  (set nbit (lt Ri 0))
  (set zbit (eq Ri 0)))

bandh - bandh #u4,@Ri

machines: base

syntax: bandh $u4,@$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-u4 f-Ri

0x8 0x1 u4 Ri

semantics:

(set QI
     (mem QI Ri)
     (and QI (or QI (sll QI u4 4) 15) (mem QI Ri)))

execution unit(s):
- fr30-1: u-exec u-load u-store

bandl - bandl #u4,@Ri

machines: base

syntax: bandl $u4,@$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-u4 f-Ri

0x8 0x0 u4 Ri

semantics:

(set QI
     (mem QI Ri)
     (and QI (or QI u4 240) (mem QI Ri)))

execution unit(s):
- fr30-1: u-exec u-load u-store

bc - bc label9

machines: base

syntax: bc $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xe 0x4 label9

semantics:
```
(if cbit (set pc label9))
```
execution unit(s):
- fr30-1: u-cti

bcd - bc:d label9

machines: base

syntax: bc:d $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xf 0x4 label9

semantics:
```
(delay 1 (if cbit (set pc label9)))
```
execution unit(s):
- fr30-1: u-cti

beorh - beorh #u4,@args

machines: base

syntax: beorh $u4,@$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-u4 f-Ri

0x9 0x9 u4 Ri

semantics:

(set QI
     (mem QI Ri)
     (xor QI (sll QI u4 4) (mem QI Ri)))

execution unit(s):
- fr30-1: u-exec u-load u-store

beorl - beorl #u4,@Ri

machines: base

syntax: beorl $u4,@$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-u4 f-Ri

0x9 0x8 u4 Ri

semantics:

(set QI (mem QI Ri) (xor QI u4 (mem QI Ri)))

execution unit(s):
- fr30-1: u-exec u-load u-store

beq - beq label9

machines: base

syntax: beq $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xe 0x2 label9

semantics:
```
(if zbit (set pc label9))
```
execution unit(s):
- fr30-1: u-cti

beqd - beq:d label9

machines: base

syntax: beq:d $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xf 0x2 label9

semantics:
```
(delay 1 (if zbit (set pc label9)))
```
execution unit(s):
- fr30-1: u-cti

bge - bge label9

machines: base

syntax: bge $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xe 0xb label9

semantics:

(if (not (xor vbit nbit)) (set pc label9))

execution unit(s):
- fr30-1: u-cti

bged - bge:d label9

machines: base

syntax: bge:d $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xf 0xb label9

semantics:

(delay 1
       (if (not (xor vbit nbit)) (set pc label9)))

execution unit(s):
- fr30-1: u-cti

bgt - bgt label9

machines: base

syntax: bgt $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xe 0xd label9

semantics:

(if (not (or (xor vbit nbit) zbit))
    (set pc label9))

execution unit(s):
- fr30-1: u-cti

bgtd - bgt:d label9

machines: base

syntax: bgt:d $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xf 0xd label9

semantics:

(delay 1
       (if (not (or (xor vbit nbit) zbit))
           (set pc label9)))

execution unit(s):
- fr30-1: u-cti

bhi - bhi label9

machines: base

syntax: bhi $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xe 0xf label9

semantics:

(if (not (or cbit zbit)) (set pc label9))

execution unit(s):
- fr30-1: u-cti

bhid - bhi:d label9

machines: base

syntax: bhi:d $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xf 0xf label9

semantics:

(delay 1
       (if (not (or cbit zbit)) (set pc label9)))

execution unit(s):
- fr30-1: u-cti

ble - ble label9

machines: base

syntax: ble $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xe 0xc label9

semantics:

(if (or (xor vbit nbit) zbit) (set pc label9))

execution unit(s):
- fr30-1: u-cti

bled - ble:d label9

machines: base

syntax: ble:d $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xf 0xc label9

semantics:

(delay 1
       (if (or (xor vbit nbit) zbit) (set pc label9)))

execution unit(s):
- fr30-1: u-cti

bls - bls label9

machines: base

syntax: bls $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xe 0xe label9

semantics:
```
(if (or cbit zbit) (set pc label9))
```
execution unit(s):
- fr30-1: u-cti

blsd - bls:d label9

machines: base

syntax: bls:d $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xf 0xe label9

semantics:

(delay 1 (if (or cbit zbit) (set pc label9)))

execution unit(s):
- fr30-1: u-cti

blt - blt label9

machines: base

syntax: blt $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xe 0xa label9

semantics:
```
(if (xor vbit nbit) (set pc label9))
```
execution unit(s):
- fr30-1: u-cti

bltd - blt:d label9

machines: base

syntax: blt:d $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xf 0xa label9

semantics:

(delay 1 (if (xor vbit nbit) (set pc label9)))

execution unit(s):
- fr30-1: u-cti

bn - bn label9

machines: base

syntax: bn $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xe 0x6 label9

semantics:
```
(if nbit (set pc label9))
```
execution unit(s):
- fr30-1: u-cti

bnc - bnc label9

machines: base

syntax: bnc $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xe 0x5 label9

semantics:
```
(if (not cbit) (set pc label9))
```
execution unit(s):
- fr30-1: u-cti

bncd - bnc:d label9

machines: base

syntax: bnc:d $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xf 0x5 label9

semantics:

(delay 1 (if (not cbit) (set pc label9)))

execution unit(s):
- fr30-1: u-cti

bnd - bn:d label9

machines: base

syntax: bn:d $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xf 0x6 label9

semantics:
```
(delay 1 (if nbit (set pc label9)))
```
execution unit(s):
- fr30-1: u-cti

bne - bne label9

machines: base

syntax: bne $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xe 0x3 label9

semantics:
```
(if (not zbit) (set pc label9))
```
execution unit(s):
- fr30-1: u-cti

bned - bne:d label9

machines: base

syntax: bne:d $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xf 0x3 label9

semantics:

(delay 1 (if (not zbit) (set pc label9)))

execution unit(s):
- fr30-1: u-cti

bno - bno label9

machines: base

syntax: bno $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xe 0x1 label9

semantics:
```
(nop)
```
execution unit(s):
- fr30-1: u-cti

bnod - bno:d label9

machines: base

syntax: bno:d $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xf 0x1 label9

semantics:
```
(delay 1 (nop))
```
execution unit(s):
- fr30-1: u-cti

bnv - bnv label9

machines: base

syntax: bnv $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xe 0x9 label9

semantics:
```
(if (not vbit) (set pc label9))
```
execution unit(s):
- fr30-1: u-cti

bnvd - bnv:d label9

machines: base

syntax: bnv:d $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xf 0x9 label9

semantics:

(delay 1 (if (not vbit) (set pc label9)))

execution unit(s):
- fr30-1: u-cti

borh - borh #u4,@args

machines: base

syntax: borh $u4,@$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-u4 f-Ri

0x9 0x1 u4 Ri

semantics:

(set QI
     (mem QI Ri)
     (or QI (sll QI u4 4) (mem QI Ri)))

execution unit(s):
- fr30-1: u-exec u-load u-store

borl - borl #u4,@Ri

machines: base

syntax: borl $u4,@$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-u4 f-Ri

0x9 0x0 u4 Ri

semantics:

(set QI (mem QI Ri) (or QI u4 (mem QI Ri)))

execution unit(s):
- fr30-1: u-exec u-load u-store

bp - bp label9

machines: base

syntax: bp $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xe 0x7 label9

semantics:
```
(if (not nbit) (set pc label9))
```
execution unit(s):
- fr30-1: u-cti

bpd - bp:d label9

machines: base

syntax: bp:d $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xf 0x7 label9

semantics:

(delay 1 (if (not nbit) (set pc label9)))

execution unit(s):
- fr30-1: u-cti

bra - bra label9

machines: base

syntax: bra $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xe 0x0 label9

semantics:
```
(set pc label9)
```
execution unit(s):
- fr30-1: u-cti

brad - bra:d label9

machines: base

syntax: bra:d $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xf 0x0 label9

semantics:
```
(delay 1 (set pc label9))
```
execution unit(s):
- fr30-1: u-cti

btsth - btsth #u4,@Ri

machines: base

syntax: btsth $u4,@$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-u4 f-Ri

0x8 0x9 u4 Ri

semantics:

(sequence
  ((QI tmp))
  (set tmp (and QI (sll QI u4 4) (mem QI Ri)))
  (set zbit (eq tmp 0))
  (set nbit (lt tmp 0)))

execution unit(s):
- fr30-1: u-load u-exec

btstl - btstl #u4,@Ri

machines: base

syntax: btstl $u4,@$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-u4 f-Ri

0x8 0x8 u4 Ri

semantics:

(sequence
  ((QI tmp))
  (set tmp (and QI u4 (mem QI Ri)))
  (set zbit (eq tmp 0))
  (set nbit 0))

execution unit(s):
- fr30-1: u-load u-exec

bv - bv label9

machines: base

syntax: bv $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xe 0x8 label9

semantics:
```
(if vbit (set pc label9))
```
execution unit(s):
- fr30-1: u-cti

bvd - bv:d label9

machines: base

syntax: bv:d $label9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-cc f-rel9

0xf 0x8 label9

semantics:
```
(delay 1 (if vbit (set pc label9)))
```
execution unit(s):
- fr30-1: u-cti

call - call relative to pc

machines: base

syntax: call $label12

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op5 f-rel12

0xd 0x0 label12

semantics:

(sequence
  ()
  (set (reg h-dr 1) (add pc 2))
  (set pc label12))

execution unit(s):
- fr30-1: u-cti

calld - call relative to pc

machines: base

syntax: call:d $label12

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op5 f-rel12

0xd 0x1 label12

semantics:

(delay 1
       (sequence
         ()
         (set (reg h-dr 1) (add pc 4))
         (set pc label12)))

execution unit(s):
- fr30-1: u-cti

callr - call @Ri

machines: base

syntax: call @$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-Ri

0x9 0x7 0x1 Ri

semantics:

(sequence
  ()
  (set (reg h-dr 1) (add pc 2))
  (set pc Ri))

execution unit(s):
- fr30-1: u-cti

callrd - call:d @Ri

machines: base

syntax: call:d @$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-Ri

0x9 0xf 0x1 Ri

semantics:

(delay 1
       (sequence
         ()
         (set (reg h-dr 1) (add pc 4))
         (set pc Ri)))

execution unit(s):
- fr30-1: u-cti

cmp - cmp reg/reg

machines: base

syntax: cmp $Rj,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0xa 0xa Rj Ri

semantics:

(sequence
  ((WI tmp1))
  (set vbit (sub-oflag Ri Rj 0))
  (set cbit (sub-cflag Ri Rj 0))
  (set tmp1 (sub Ri Rj))
  (sequence
    ()
    (set zbit (eq tmp1 0))
    (set nbit (lt tmp1 0))))

cmp2 - cmp2 immed/reg

machines: base

syntax: cmp2 $m4,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-m4 f-Ri

0xa 0x9 m4 Ri

semantics:

(sequence
  ((WI tmp1))
  (set vbit (sub-oflag Ri m4 0))
  (set cbit (sub-cflag Ri m4 0))
  (set tmp1 (sub Ri m4))
  (sequence
    ()
    (set zbit (eq tmp1 0))
    (set nbit (lt tmp1 0))))

cmpi - cmp immed/reg

machines: base

syntax: cmp $u4,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-u4 f-Ri

0xa 0x8 u4 Ri

semantics:

(sequence
  ((WI tmp1))
  (set vbit (sub-oflag Ri u4 0))
  (set cbit (sub-cflag Ri u4 0))
  (set tmp1 (sub Ri u4))
  (sequence
    ()
    (set zbit (eq tmp1 0))
    (set nbit (lt tmp1 0))))

copld - copld u4c,ccc,CRj,Rjc,CRi

machines: base

syntax: copld $u4c,$ccc,$Rjc,$CRi

format:

0 1 2 3	4 5 6 7 8 9 10 11	12 13 14 15	16 17 18 19	20 21 22 23	24 25 26 27	28 29 30 31
f-op1	f-ccc	f-op2	f-op3	f-Rjc	f-u4c	f-CRi
0x9	ccc	0xf	0xd	Rjc	u4c	CRi

semantics:
```
(nop)
```

copop - copop u4c,ccc,CRj,CRj,CRi

machines: base

syntax: copop $u4c,$ccc,$CRj,$CRi

format:

0 1 2 3	4 5 6 7 8 9 10 11	12 13 14 15	16 17 18 19	20 21 22 23	24 25 26 27	28 29 30 31
f-op1	f-ccc	f-op2	f-op3	f-CRj	f-u4c	f-CRi
0x9	ccc	0xf	0xc	CRj	u4c	CRi

semantics:
```
(nop)
```

copst - copst u4c,ccc,CRj,CRj,Ric

machines: base

syntax: copst $u4c,$ccc,$CRj,$Ric

format:

0 1 2 3	4 5 6 7 8 9 10 11	12 13 14 15	16 17 18 19	20 21 22 23	24 25 26 27	28 29 30 31
f-op1	f-ccc	f-op2	f-op3	f-CRj	f-u4c	f-Ric
0x9	ccc	0xf	0xe	CRj	u4c	Ric

semantics:
```
(nop)
```

copsv - copsv u4c,ccc,CRj,CRj,Ric

machines: base

syntax: copsv $u4c,$ccc,$CRj,$Ric

format:

0 1 2 3	4 5 6 7 8 9 10 11	12 13 14 15	16 17 18 19	20 21 22 23	24 25 26 27	28 29 30 31
f-op1	f-ccc	f-op2	f-op3	f-CRj	f-u4c	f-Ric
0x9	ccc	0xf	0xf	CRj	u4c	Ric

semantics:
```
(nop)
```

div0s - div0s Ri

machines: base

syntax: div0s $Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-Ri

0x9 0x7 0x4 Ri

semantics:

(sequence
  ()
  (set d0bit (lt (reg h-dr 5) 0))
  (set d1bit (xor d0bit (lt Ri 0)))
  (if (ne d0bit 0)
      (set (reg h-dr 4) 4294967295)
      (set (reg h-dr 4) 0)))

div0u - div0u Ri

machines: base

syntax: div0u $Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-Ri

0x9 0x7 0x5 Ri

semantics:

(sequence
  ()
  (set d0bit 0)
  (set d1bit 0)
  (set (reg h-dr 4) 0))

div1 - div1 Ri

machines: base

syntax: div1 $Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-Ri

0x9 0x7 0x6 Ri

semantics:

(sequence
  ((WI tmp))
  (set (reg h-dr 4) (sll (reg h-dr 4) 1))
  (if (lt (reg h-dr 5) 0)
      (set (reg h-dr 4) (add (reg h-dr 4) 1)))
  (set (reg h-dr 5) (sll (reg h-dr 5) 1))
  (if (eq d1bit 1)
      (sequence
        ()
        (set tmp (add (reg h-dr 4) Ri))
        (set cbit (add-cflag (reg h-dr 4) Ri 0)))
      (sequence
        ()
        (set tmp (sub (reg h-dr 4) Ri))
        (set cbit (sub-cflag (reg h-dr 4) Ri 0))))
  (if (not (xor (xor d0bit d1bit) cbit))
      (sequence
        ()
        (set (reg h-dr 4) tmp)
        (set (reg h-dr 5) (or (reg h-dr 5) 1))))
  (set zbit (eq (reg h-dr 4) 0)))

div2 - div2 Ri

machines: base

syntax: div2 $Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-Ri

0x9 0x7 0x7 Ri

semantics:

(sequence
  ((WI tmp))
  (if (eq d1bit 1)
      (sequence
        ()
        (set tmp (add (reg h-dr 4) Ri))
        (set cbit (add-cflag (reg h-dr 4) Ri 0)))
      (sequence
        ()
        (set tmp (sub (reg h-dr 4) Ri))
        (set cbit (sub-cflag (reg h-dr 4) Ri 0))))
  (if (eq tmp 0)
      (sequence () (set zbit 1) (set (reg h-dr 4) 0))
      (set zbit 0)))

div3 - div3

machines: base

syntax: div3

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-op4

0x9 0xf 0x6 0x0

semantics:

(if (eq zbit 1)
    (set (reg h-dr 5) (add (reg h-dr 5) 1)))

div4s - div4s

machines: base

syntax: div4s

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-op4

0x9 0xf 0x7 0x0

semantics:

(if (eq d1bit 1)
    (set (reg h-dr 5) (neg (reg h-dr 5))))

dmov2r13 - dmov @dir10,R13

machines: base

syntax: dmov @$dir10,$R13

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-dir10

0x0 0x8 dir10

semantics:
```
(set (reg h-gr 13) (mem WI dir10))
```
execution unit(s):
- fr30-1: u-load

dmov2r13b - dmovb @dir8,R13

machines: base

syntax: dmovb @$dir8,$R13

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-dir8

0x0 0xa dir8

semantics:
```
(set (reg h-gr 13) (mem QI dir8))
```
execution unit(s):
- fr30-1: u-load

dmov2r13h - dmovh @dir9,R13

machines: base

syntax: dmovh @$dir9,$R13

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-dir9

0x0 0x9 dir9

semantics:
```
(set (reg h-gr 13) (mem HI dir9))
```
execution unit(s):
- fr30-1: u-load

dmov2r13pi - dmov @dir10,@R13+

machines: base

syntax: dmov @$dir10,@$R13+

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-dir10

0x0 0xc dir10

semantics:

(sequence
  ()
  (set (mem WI (reg h-gr 13)) (mem WI dir10))
  (set (reg h-gr 13) (add (reg h-gr 13) 4)))

execution unit(s):
- fr30-1: u-load u-store

dmov2r13pib - dmovb @dir8,@R13+

machines: base

syntax: dmovb @$dir8,@$R13+

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-dir8

0x0 0xe dir8

semantics:

(sequence
  ()
  (set (mem QI (reg h-gr 13)) (mem QI dir8))
  (set (reg h-gr 13) (add (reg h-gr 13) 1)))

execution unit(s):
- fr30-1: u-load u-store

dmov2r13pih - dmovh @dir9,@R13+

machines: base

syntax: dmovh @$dir9,@$R13+

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-dir9

0x0 0xd dir9

semantics:

(sequence
  ()
  (set (mem HI (reg h-gr 13)) (mem HI dir9))
  (set (reg h-gr 13) (add (reg h-gr 13) 2)))

execution unit(s):
- fr30-1: u-load u-store

dmov2r15pd - dmov @dir10,@-R15

machines: base

syntax: dmov @$dir10,@-$R15

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-dir10

0x0 0xb dir10

semantics:

(sequence
  ()
  (set (reg h-gr 15) (sub (reg h-gr 15) 4))
  (set (mem WI (reg h-gr 15)) (mem WI dir10)))

execution unit(s):
- fr30-1: u-load u-store

dmovr13 - dmov R13,@dir10

machines: base

syntax: dmov $R13,@$dir10

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-dir10

0x1 0x8 dir10

semantics:
```
(set (mem WI dir10) (reg h-gr 13))
```
execution unit(s):
- fr30-1: u-store

dmovr13b - dmovb R13,@dir8

machines: base

syntax: dmovb $R13,@$dir8

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-dir8

0x1 0xa dir8

semantics:
```
(set (mem QI dir8) (reg h-gr 13))
```
execution unit(s):
- fr30-1: u-store

dmovr13h - dmovh R13,@dir9

machines: base

syntax: dmovh $R13,@$dir9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-dir9

0x1 0x9 dir9

semantics:
```
(set (mem HI dir9) (reg h-gr 13))
```
execution unit(s):
- fr30-1: u-store

dmovr13pi - dmov @R13+,@dir10

machines: base

syntax: dmov @$R13+,@$dir10

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-dir10

0x1 0xc dir10

semantics:

(sequence
  ()
  (set (mem WI dir10) (mem WI (reg h-gr 13)))
  (set (reg h-gr 13) (add (reg h-gr 13) 4)))

execution unit(s):
- fr30-1: u-load u-store

dmovr13pib - dmovb @R13+,@dir8

machines: base

syntax: dmovb @$R13+,@$dir8

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-dir8

0x1 0xe dir8

semantics:

(sequence
  ()
  (set (mem QI dir8) (mem QI (reg h-gr 13)))
  (set (reg h-gr 13) (add (reg h-gr 13) 1)))

execution unit(s):
- fr30-1: u-load u-store

dmovr13pih - dmovh @R13+,@dir9

machines: base

syntax: dmovh @$R13+,@$dir9

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-dir9

0x1 0xd dir9

semantics:

(sequence
  ()
  (set (mem HI dir9) (mem HI (reg h-gr 13)))
  (set (reg h-gr 13) (add (reg h-gr 13) 2)))

execution unit(s):
- fr30-1: u-load u-store

dmovr15pi - dmov @R15+,@dir10

machines: base

syntax: dmov @$R15+,@$dir10

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-dir10

0x1 0xb dir10

semantics:

(sequence
  ()
  (set (mem WI dir10) (mem WI (reg h-gr 15)))
  (set (reg h-gr 15) (add (reg h-gr 15) 4)))

execution unit(s):
- fr30-1: u-load u-store

enter - enter #u10

machines: base

syntax: enter $u10

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-u10

0x0 0xf u10

semantics:

(sequence
  ((WI tmp))
  (set tmp (sub (reg h-gr 15) 4))
  (set (mem WI tmp) (reg h-gr 14))
  (set (reg h-gr 14) tmp)
  (set (reg h-gr 15) (sub (reg h-gr 15) u10)))

execution unit(s):
- fr30-1: u-exec

eor - eor reg/reg

machines: base

syntax: eor $Rj,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x9 0xa Rj Ri

semantics:

(sequence
  ()
  (set Ri (xor Ri Rj))
  (sequence
    ()
    (set zbit (eq Ri 0))
    (set nbit (lt Ri 0))))

eorb - eorb reg/mem

machines: base

syntax: eorb $Rj,@$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x9 0xe Rj Ri

semantics:

(sequence
  ((QI tmp))
  (set QI tmp (xor QI (mem QI Ri) Rj))
  (sequence
    ()
    (set zbit (eq tmp 0))
    (set nbit (lt tmp 0)))
  (set QI (mem QI Ri) tmp))

execution unit(s):
- fr30-1: u-exec u-load u-store

eorh - eorh reg/mem

machines: base

syntax: eorh $Rj,@$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x9 0xd Rj Ri

semantics:

(sequence
  ((HI tmp))
  (set HI tmp (xor HI (mem HI Ri) Rj))
  (sequence
    ()
    (set zbit (eq tmp 0))
    (set nbit (lt tmp 0)))
  (set HI (mem HI Ri) tmp))

execution unit(s):
- fr30-1: u-exec u-load u-store

eorm - eor reg/mem

machines: base

syntax: eor $Rj,@$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x9 0xc Rj Ri

semantics:

(sequence
  ((WI tmp))
  (set WI tmp (xor WI (mem WI Ri) Rj))
  (sequence
    ()
    (set zbit (eq tmp 0))
    (set nbit (lt tmp 0)))
  (set WI (mem WI Ri) tmp))

execution unit(s):
- fr30-1: u-exec u-load u-store

extsb - extsb Ri

machines: base

syntax: extsb $Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-Ri

0x9 0x7 0x8 Ri

semantics:
```
(set Ri (ext WI (and QI Ri 255)))
```

extsh - extsh Ri

machines: base

syntax: extsh $Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-Ri

0x9 0x7 0xa Ri

semantics:
```
(set Ri (ext WI (and HI Ri 65535)))
```

extub - extub Ri

machines: base

syntax: extub $Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-Ri

0x9 0x7 0x9 Ri

semantics:
```
(set Ri (zext WI (and UQI Ri 255)))
```

extuh - extuh Ri

machines: base

syntax: extuh $Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-Ri

0x9 0x7 0xb Ri

semantics:
```
(set Ri (zext WI (and UHI Ri 65535)))
```

int - interrupt

machines: base

syntax: int $u8

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-u8

0x1 0xf u8

semantics:

(sequence
  ()
  (clobber (reg h-dr 2))
  (clobber ibit)
  (clobber sbit)
  (set WI pc (c-call WI "fr30_int" pc u8)))

execution unit(s):
- fr30-1: u-exec

inte - interrupt for emulator

machines: base

syntax: inte

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-op4

0x9 0xf 0x3 0x0

semantics:

(sequence
  ()
  (clobber (reg h-dr 2))
  (clobber ibit)
  (clobber ilm)
  (set WI pc (c-call WI "fr30_inte" pc)))

execution unit(s):
- fr30-1: u-exec

jmp - jmp with no delay slot

machines: base

syntax: jmp @$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-Ri

0x9 0x7 0x0 Ri

semantics:
```
(set pc Ri)
```
execution unit(s):
- fr30-1: u-cti

jmpd - jmp with delay slot

machines: base

syntax: jmp:d @$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-Ri

0x9 0xf 0x0 Ri

semantics:
```
(delay 1 (set pc Ri))
```
execution unit(s):
- fr30-1: u-cti

ld - ld @Rj,Ri

machines: base

syntax: ld @$Rj,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x0 0x4 Rj Ri

semantics:
```
(set Ri (mem WI Rj))
```
execution unit(s):
- fr30-1: u-load

ldi20 - load 20 bit unsigned immediate

machines: base

syntax: ldi:20 $i20,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

f-op1 f-i20 f-op2 f-Ri

0x9 i20 0xb Ri

semantics:
```
(set Ri i20)
```
execution unit(s):
- fr30-1: u-exec

ldi32 - load 32 bit immediate

machines: base

syntax: ldi:32 $i32,$Ri

format:

0 1 2 3	4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35	36 37 38 39	40 41 42 43	44 45 46 47
f-op1	f-i32	f-op2	f-op3	f-Ri
0x9	i32	0xf	0x8	Ri

semantics:
```
(set Ri i32)
```
execution unit(s):
- fr30-1: u-exec

ldi8 - load 8 bit unsigned immediate

machines: base

syntax: ldi:8 $i8,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-i8 f-Ri

0xc i8 Ri

semantics:
```
(set Ri i8)
```

ldm0 - ldm0 (reglist_low_ld)

machines: base

syntax: ldm0 ($reglist_low_ld)

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-reglist_low_ld

0x8 0xc reglist_low_ld

semantics:

(sequence
  ()
  (if (and reglist_low_ld 1)
      (sequence
        ()
        (set (reg h-gr 0) (mem WI (reg h-gr 15)))
        (set (reg h-gr 15) (add (reg h-gr 15) 4))))
  (if (and reglist_low_ld 2)
      (sequence
        ()
        (set (reg h-gr 1) (mem WI (reg h-gr 15)))
        (set (reg h-gr 15) (add (reg h-gr 15) 4))))
  (if (and reglist_low_ld 4)
      (sequence
        ()
        (set (reg h-gr 2) (mem WI (reg h-gr 15)))
        (set (reg h-gr 15) (add (reg h-gr 15) 4))))
  (if (and reglist_low_ld 8)
      (sequence
        ()
        (set (reg h-gr 3) (mem WI (reg h-gr 15)))
        (set (reg h-gr 15) (add (reg h-gr 15) 4))))
  (if (and reglist_low_ld 16)
      (sequence
        ()
        (set (reg h-gr 4) (mem WI (reg h-gr 15)))
        (set (reg h-gr 15) (add (reg h-gr 15) 4))))
  (if (and reglist_low_ld 32)
      (sequence
        ()
        (set (reg h-gr 5) (mem WI (reg h-gr 15)))
        (set (reg h-gr 15) (add (reg h-gr 15) 4))))
  (if (and reglist_low_ld 64)
      (sequence
        ()
        (set (reg h-gr 6) (mem WI (reg h-gr 15)))
        (set (reg h-gr 15) (add (reg h-gr 15) 4))))
  (if (and reglist_low_ld 128)
      (sequence
        ()
        (set (reg h-gr 7) (mem WI (reg h-gr 15)))
        (set (reg h-gr 15) (add (reg h-gr 15) 4)))))

execution unit(s):
- fr30-1: u-ldm

ldm1 - ldm1 (reglist_hi_ld)

machines: base

syntax: ldm1 ($reglist_hi_ld)

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-reglist_hi_ld

0x8 0xd reglist_hi_ld

semantics:

(sequence
  ()
  (if (and reglist_hi_ld 1)
      (sequence
        ()
        (set (reg h-gr 8) (mem WI (reg h-gr 15)))
        (set (reg h-gr 15) (add (reg h-gr 15) 4))))
  (if (and reglist_hi_ld 2)
      (sequence
        ()
        (set (reg h-gr 9) (mem WI (reg h-gr 15)))
        (set (reg h-gr 15) (add (reg h-gr 15) 4))))
  (if (and reglist_hi_ld 4)
      (sequence
        ()
        (set (reg h-gr 10) (mem WI (reg h-gr 15)))
        (set (reg h-gr 15) (add (reg h-gr 15) 4))))
  (if (and reglist_hi_ld 8)
      (sequence
        ()
        (set (reg h-gr 11) (mem WI (reg h-gr 15)))
        (set (reg h-gr 15) (add (reg h-gr 15) 4))))
  (if (and reglist_hi_ld 16)
      (sequence
        ()
        (set (reg h-gr 12) (mem WI (reg h-gr 15)))
        (set (reg h-gr 15) (add (reg h-gr 15) 4))))
  (if (and reglist_hi_ld 32)
      (sequence
        ()
        (set (reg h-gr 13) (mem WI (reg h-gr 15)))
        (set (reg h-gr 15) (add (reg h-gr 15) 4))))
  (if (and reglist_hi_ld 64)
      (sequence
        ()
        (set (reg h-gr 14) (mem WI (reg h-gr 15)))
        (set (reg h-gr 15) (add (reg h-gr 15) 4))))
  (if (and reglist_hi_ld 128)
      (set (reg h-gr 15) (mem WI (reg h-gr 15)))))

execution unit(s):
- fr30-1: u-ldm

ldr13 - ld @(R13,Rj),Ri

machines: base

syntax: ld @($R13,$Rj),$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x0 0x0 Rj Ri

semantics:

(set Ri (mem WI (add Rj (reg h-gr 13))))

execution unit(s):
- fr30-1: u-load

ldr13ub - ldub @(R13,Rj),Ri

machines: base

syntax: ldub @($R13,$Rj),$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x0 0x2 Rj Ri

semantics:

(set Ri (mem UQI (add Rj (reg h-gr 13))))

execution unit(s):
- fr30-1: u-load

ldr13uh - lduh @(R13,Rj),Ri

machines: base

syntax: lduh @($R13,$Rj),$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x0 0x1 Rj Ri

semantics:

(set Ri (mem UHI (add Rj (reg h-gr 13))))

execution unit(s):
- fr30-1: u-load

ldr14 - ld @(R14,disp10),Ri

machines: base

syntax: ld @($R14,$disp10),$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-disp10 f-Ri

0x2 disp10 Ri

semantics:

(set Ri (mem WI (add disp10 (reg h-gr 14))))

execution unit(s):
- fr30-1: u-load

ldr14ub - ldub @(R14,disp8),Ri

machines: base

syntax: ldub @($R14,$disp8),$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-disp8 f-Ri

0x6 disp8 Ri

semantics:

(set Ri (mem UQI (add disp8 (reg h-gr 14))))

execution unit(s):
- fr30-1: u-load

ldr14uh - lduh @(R14,disp9),Ri

machines: base

syntax: lduh @($R14,$disp9),$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-disp9 f-Ri

0x4 disp9 Ri

semantics:

(set Ri (mem UHI (add disp9 (reg h-gr 14))))

execution unit(s):
- fr30-1: u-load

ldr15 - ld @(R15,udisp6),Ri mem/reg

machines: base

syntax: ld @($R15,$udisp6),$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-udisp6 f-Ri

0x0 0x3 udisp6 Ri

semantics:

(set Ri (mem WI (add udisp6 (reg h-gr 15))))

execution unit(s):
- fr30-1: u-load

ldr15dr - ld @R15+,Rs2

machines: base

syntax: ld @$R15+,$Rs2

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-Rs2

0x0 0x7 0x8 Rs2

semantics:

(sequence
  ((WI tmp))
  (set tmp (mem WI (reg h-gr 15)))
  (set (reg h-gr 15) (add (reg h-gr 15) 4))
  (set Rs2 tmp))

execution unit(s):
- fr30-1: u-load

ldr15gr - ld @R15+,Ri

machines: base

syntax: ld @$R15+,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-Ri

0x0 0x7 0x0 Ri

semantics:

(sequence
  ()
  (set Ri (mem WI (reg h-gr 15)))
  (if (ne f-Ri 15)
      (set (reg h-gr 15) (add (reg h-gr 15) 4))))

execution unit(s):
- fr30-1: u-load

ldr15ps - ld @R15+,ps mem/reg

machines: base

syntax: ld @$R15+,$ps

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-op4

0x0 0x7 0x9 0x0

semantics:

(sequence
  ()
  (set ps (mem WI (reg h-gr 15)))
  (set (reg h-gr 15) (add (reg h-gr 15) 4)))

execution unit(s):
- fr30-1: u-load

ldres - ldres @Ri+,#u4

machines: base

syntax: ldres @$Ri+,$u4

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-u4 f-Ri

0xb 0xc u4 Ri

semantics:
```
(set Ri (add Ri 4))
```

ldub - ldub @Rj,Ri

machines: base

syntax: ldub @$Rj,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x0 0x6 Rj Ri

semantics:
```
(set Ri (mem UQI Rj))
```
execution unit(s):
- fr30-1: u-load

lduh - lduh @Rj,Ri

machines: base

syntax: lduh @$Rj,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x0 0x5 Rj Ri

semantics:
```
(set Ri (mem UHI Rj))
```
execution unit(s):
- fr30-1: u-load

leave - leave

machines: base

syntax: leave

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-op4

0x9 0xf 0x9 0x0

semantics:

(sequence
  ()
  (set (reg h-gr 15) (add (reg h-gr 14) 4))
  (set (reg h-gr 14)
       (mem WI (sub (reg h-gr 15) 4))))

lsl - lsl Rj,Ri

machines: base

syntax: lsl $Rj,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0xb 0x6 Rj Ri

semantics:

(sequence
  ((WI shift))
  (set shift (and Rj 31))
  (if (ne shift 0)
      (sequence
        ()
        (set cbit (ne (and Ri (sll 1 (sub 32 shift))) 0))
        (set Ri (sll Ri shift)))
      (set cbit 0))
  (set nbit (lt Ri 0))
  (set zbit (eq Ri 0)))

lsl2 - lsl2 u4,Ri

machines: base

syntax: lsl2 $u4,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-u4 f-Ri

0xb 0x5 u4 Ri

semantics:

(sequence
  ((WI shift))
  (set shift (add u4 16))
  (if (ne shift 0)
      (sequence
        ()
        (set cbit (ne (and Ri (sll 1 (sub 32 shift))) 0))
        (set Ri (sll Ri shift)))
      (set cbit 0))
  (set nbit (lt Ri 0))
  (set zbit (eq Ri 0)))

lsli - lsl u4,Ri

machines: base

syntax: lsl $u4,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-u4 f-Ri

0xb 0x4 u4 Ri

semantics:

(sequence
  ((WI shift))
  (set shift u4)
  (if (ne shift 0)
      (sequence
        ()
        (set cbit (ne (and Ri (sll 1 (sub 32 shift))) 0))
        (set Ri (sll Ri shift)))
      (set cbit 0))
  (set nbit (lt Ri 0))
  (set zbit (eq Ri 0)))

lsr - lsr Rj,Ri

machines: base

syntax: lsr $Rj,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0xb 0x2 Rj Ri

semantics:

(sequence
  ((WI shift))
  (set shift (and Rj 31))
  (if (ne shift 0)
      (sequence
        ()
        (set cbit (ne (and Ri (sll 1 (sub shift 1))) 0))
        (set Ri (srl Ri shift)))
      (set cbit 0))
  (set nbit (lt Ri 0))
  (set zbit (eq Ri 0)))

lsr2 - lsr2 u4,Ri

machines: base

syntax: lsr2 $u4,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-u4 f-Ri

0xb 0x1 u4 Ri

semantics:

(sequence
  ((WI shift))
  (set shift (add u4 16))
  (if (ne shift 0)
      (sequence
        ()
        (set cbit (ne (and Ri (sll 1 (sub shift 1))) 0))
        (set Ri (srl Ri shift)))
      (set cbit 0))
  (set nbit (lt Ri 0))
  (set zbit (eq Ri 0)))

lsri - lsr u4,Ri

machines: base

syntax: lsr $u4,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-u4 f-Ri

0xb 0x0 u4 Ri

semantics:

(sequence
  ((WI shift))
  (set shift u4)
  (if (ne shift 0)
      (sequence
        ()
        (set cbit (ne (and Ri (sll 1 (sub shift 1))) 0))
        (set Ri (srl Ri shift)))
      (set cbit 0))
  (set nbit (lt Ri 0))
  (set zbit (eq Ri 0)))

mov - mov Rj,Ri

machines: base

syntax: mov $Rj,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x8 0xb Rj Ri

semantics:
```
(set Ri Rj)
```

mov2dr - mov Ri,Rs reg/reg

machines: base

syntax: mov $Ri,$Rs1

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rs1 f-Ri

0xb 0x3 Rs1 Ri

semantics:
```
(set Rs1 Ri)
```

mov2ps - mov Ri,ps reg/reg

machines: base

syntax: mov $Ri,$ps

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-Ri

0x0 0x7 0x1 Ri

semantics:
```
(set ps Ri)
```

movdr - mov Rs1,Ri

machines: base

syntax: mov $Rs1,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rs1 f-Ri

0xb 0x7 Rs1 Ri

semantics:
```
(set Ri Rs1)
```

movps - mov ps,Ri reg/reg

machines: base

syntax: mov $ps,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-Ri

0x1 0x7 0x1 Ri

semantics:
```
(set Ri ps)
```

mul - mul Rj,Ri

machines: base

syntax: mul $Rj,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0xa 0xf Rj Ri

semantics:

(sequence
  ((DI tmp))
  (set tmp (mul DI (ext DI Rj) (ext DI Ri)))
  (set (reg h-dr 5) (trunc WI tmp))
  (set (reg h-dr 4) (trunc WI (srl tmp 32)))
  (set nbit (lt (reg h-dr 5) 0))
  (set zbit (eq tmp 0))
  (set vbit
       (orif (gt tmp 2147483647)
             (lt tmp (neg 2147483648)))))

execution unit(s):
- fr30-1: u-exec

mulh - mulh Rj,Ri

machines: base

syntax: mulh $Rj,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0xb 0xf Rj Ri

semantics:

(sequence
  ()
  (set (reg h-dr 5)
       (mul (trunc HI Rj) (trunc HI Ri)))
  (set nbit (lt (reg h-dr 5) 0))
  (set zbit (ge (reg h-dr 5) 0)))

execution unit(s):
- fr30-1: u-exec

mulu - mulu Rj,Ri

machines: base

syntax: mulu $Rj,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0xa 0xb Rj Ri

semantics:

(sequence
  ((DI tmp))
  (set tmp (mul DI (zext DI Rj) (zext DI Ri)))
  (set (reg h-dr 5) (trunc WI tmp))
  (set (reg h-dr 4) (trunc WI (srl tmp 32)))
  (set nbit (lt (reg h-dr 4) 0))
  (set zbit (eq (reg h-dr 5) 0))
  (set vbit (ne (reg h-dr 4) 0)))

execution unit(s):
- fr30-1: u-exec

muluh - muluh Rj,Ri

machines: base

syntax: muluh $Rj,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0xb 0xb Rj Ri

semantics:

(sequence
  ()
  (set (reg h-dr 5)
       (mul (and Rj 65535) (and Ri 65535)))
  (set nbit (lt (reg h-dr 5) 0))
  (set zbit (ge (reg h-dr 5) 0)))

execution unit(s):
- fr30-1: u-exec

nop - nop

machines: base

syntax: nop

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-op4

0x9 0xf 0xa 0x0

semantics:
```
(nop)
```

or - or reg/reg

machines: base

syntax: or $Rj,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x9 0x2 Rj Ri

semantics:

(sequence
  ()
  (set Ri (or Ri Rj))
  (sequence
    ()
    (set zbit (eq Ri 0))
    (set nbit (lt Ri 0))))

orb - orb reg/mem

machines: base

syntax: orb $Rj,@$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x9 0x6 Rj Ri

semantics:

(sequence
  ((QI tmp))
  (set QI tmp (or QI (mem QI Ri) Rj))
  (sequence
    ()
    (set zbit (eq tmp 0))
    (set nbit (lt tmp 0)))
  (set QI (mem QI Ri) tmp))

execution unit(s):
- fr30-1: u-exec u-load u-store

orccr - orccr #u8

machines: base

syntax: orccr $u8

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-u8

0x9 0x3 u8

semantics:
```
(set ccr (or ccr u8))
```

orh - orh reg/mem

machines: base

syntax: orh $Rj,@$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x9 0x5 Rj Ri

semantics:

(sequence
  ((HI tmp))
  (set HI tmp (or HI (mem HI Ri) Rj))
  (sequence
    ()
    (set zbit (eq tmp 0))
    (set nbit (lt tmp 0)))
  (set HI (mem HI Ri) tmp))

execution unit(s):
- fr30-1: u-exec u-load u-store

orm - or reg/mem

machines: base

syntax: or $Rj,@$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x9 0x4 Rj Ri

semantics:

(sequence
  ((WI tmp))
  (set WI tmp (or WI (mem WI Ri) Rj))
  (sequence
    ()
    (set zbit (eq tmp 0))
    (set nbit (lt tmp 0)))
  (set WI (mem WI Ri) tmp))

execution unit(s):
- fr30-1: u-exec u-load u-store

ret - return from subroutine

machines: base

syntax: ret

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-op4

0x9 0x7 0x2 0x0

semantics:
```
(set pc (reg h-dr 1))
```
execution unit(s):
- fr30-1: u-cti

ret:d - return from subroutine with delay slot

machines: base

syntax: ret:d

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-op4

0x9 0xf 0x2 0x0

semantics:
```
(delay 1 (set pc (reg h-dr 1)))
```
execution unit(s):
- fr30-1: u-cti

reti - return from interrupt

machines: base

syntax: reti

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-op4

0x9 0x7 0x3 0x0

semantics:

(if (eq sbit 0)
    (sequence
      ()
      (set UWI pc (mem UWI (reg h-dr 2)))
      (set (reg h-dr 2) (add (reg h-dr 2) 4))
      (set UWI ps (mem UWI (reg h-dr 2)))
      (set (reg h-dr 2) (add (reg h-dr 2) 4)))
    (sequence
      ()
      (set UWI pc (mem UWI (reg h-dr 3)))
      (set (reg h-dr 3) (add (reg h-dr 3) 4))
      (set UWI ps (mem UWI (reg h-dr 3)))
      (set (reg h-dr 3) (add (reg h-dr 3) 4))))

execution unit(s):
- fr30-1: u-exec

st - st Ri,@Rj

machines: base

syntax: st $Ri,@$Rj

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x1 0x4 Rj Ri

semantics:
```
(set (mem WI Rj) Ri)
```
execution unit(s):
- fr30-1: u-store

stb - stb Ri,@Rj

machines: base

syntax: stb $Ri,@$Rj

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x1 0x6 Rj Ri

semantics:
```
(set (mem QI Rj) Ri)
```
execution unit(s):
- fr30-1: u-store

sth - sth Ri,@Rj

machines: base

syntax: sth $Ri,@$Rj

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x1 0x5 Rj Ri

semantics:
```
(set (mem HI Rj) Ri)
```
execution unit(s):
- fr30-1: u-store

stilm - stilm #u8

machines: base

syntax: stilm $u8

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-u8

0x8 0x7 u8

semantics:
```
(set ilm (and u8 31))
```

stm0 - stm0 (reglist_low_st)

machines: base

syntax: stm0 ($reglist_low_st)

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-reglist_low_st

0x8 0xe reglist_low_st

semantics:

(sequence
  ()
  (if (and reglist_low_st 1)
      (sequence
        ()
        (set (reg h-gr 15) (sub (reg h-gr 15) 4))
        (set (mem WI (reg h-gr 15)) (reg h-gr 7))))
  (if (and reglist_low_st 2)
      (sequence
        ()
        (set (reg h-gr 15) (sub (reg h-gr 15) 4))
        (set (mem WI (reg h-gr 15)) (reg h-gr 6))))
  (if (and reglist_low_st 4)
      (sequence
        ()
        (set (reg h-gr 15) (sub (reg h-gr 15) 4))
        (set (mem WI (reg h-gr 15)) (reg h-gr 5))))
  (if (and reglist_low_st 8)
      (sequence
        ()
        (set (reg h-gr 15) (sub (reg h-gr 15) 4))
        (set (mem WI (reg h-gr 15)) (reg h-gr 4))))
  (if (and reglist_low_st 16)
      (sequence
        ()
        (set (reg h-gr 15) (sub (reg h-gr 15) 4))
        (set (mem WI (reg h-gr 15)) (reg h-gr 3))))
  (if (and reglist_low_st 32)
      (sequence
        ()
        (set (reg h-gr 15) (sub (reg h-gr 15) 4))
        (set (mem WI (reg h-gr 15)) (reg h-gr 2))))
  (if (and reglist_low_st 64)
      (sequence
        ()
        (set (reg h-gr 15) (sub (reg h-gr 15) 4))
        (set (mem WI (reg h-gr 15)) (reg h-gr 1))))
  (if (and reglist_low_st 128)
      (sequence
        ()
        (set (reg h-gr 15) (sub (reg h-gr 15) 4))
        (set (mem WI (reg h-gr 15)) (reg h-gr 0)))))

execution unit(s):
- fr30-1: u-stm

stm1 - stm1 (reglist_hi_st)

machines: base

syntax: stm1 ($reglist_hi_st)

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-reglist_hi_st

0x8 0xf reglist_hi_st

semantics:

(sequence
  ()
  (if (and reglist_hi_st 1)
      (sequence
        ((WI save-r15))
        (set save-r15 (reg h-gr 15))
        (set (reg h-gr 15) (sub (reg h-gr 15) 4))
        (set (mem WI (reg h-gr 15)) save-r15)))
  (if (and reglist_hi_st 2)
      (sequence
        ()
        (set (reg h-gr 15) (sub (reg h-gr 15) 4))
        (set (mem WI (reg h-gr 15)) (reg h-gr 14))))
  (if (and reglist_hi_st 4)
      (sequence
        ()
        (set (reg h-gr 15) (sub (reg h-gr 15) 4))
        (set (mem WI (reg h-gr 15)) (reg h-gr 13))))
  (if (and reglist_hi_st 8)
      (sequence
        ()
        (set (reg h-gr 15) (sub (reg h-gr 15) 4))
        (set (mem WI (reg h-gr 15)) (reg h-gr 12))))
  (if (and reglist_hi_st 16)
      (sequence
        ()
        (set (reg h-gr 15) (sub (reg h-gr 15) 4))
        (set (mem WI (reg h-gr 15)) (reg h-gr 11))))
  (if (and reglist_hi_st 32)
      (sequence
        ()
        (set (reg h-gr 15) (sub (reg h-gr 15) 4))
        (set (mem WI (reg h-gr 15)) (reg h-gr 10))))
  (if (and reglist_hi_st 64)
      (sequence
        ()
        (set (reg h-gr 15) (sub (reg h-gr 15) 4))
        (set (mem WI (reg h-gr 15)) (reg h-gr 9))))
  (if (and reglist_hi_st 128)
      (sequence
        ()
        (set (reg h-gr 15) (sub (reg h-gr 15) 4))
        (set (mem WI (reg h-gr 15)) (reg h-gr 8)))))

execution unit(s):
- fr30-1: u-stm

str13 - st Ri,@(R13,Rj)

machines: base

syntax: st $Ri,@($R13,$Rj)

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x1 0x0 Rj Ri

semantics:

(set (mem WI (add Rj (reg h-gr 13))) Ri)

execution unit(s):
- fr30-1: u-store

str13b - stb Ri,@(R13,Rj)

machines: base

syntax: stb $Ri,@($R13,$Rj)

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x1 0x2 Rj Ri

semantics:

(set (mem QI (add Rj (reg h-gr 13))) Ri)

execution unit(s):
- fr30-1: u-store

str13h - sth Ri,@(R13,Rj)

machines: base

syntax: sth $Ri,@($R13,$Rj)

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x1 0x1 Rj Ri

semantics:

(set (mem HI (add Rj (reg h-gr 13))) Ri)

execution unit(s):
- fr30-1: u-store

str14 - st Ri,@(R14,disp10)

machines: base

syntax: st $Ri,@($R14,$disp10)

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-disp10 f-Ri

0x3 disp10 Ri

semantics:

(set (mem WI (add disp10 (reg h-gr 14))) Ri)

execution unit(s):
- fr30-1: u-store

str14b - stb Ri,@(R14,disp8)

machines: base

syntax: stb $Ri,@($R14,$disp8)

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-disp8 f-Ri

0x7 disp8 Ri

semantics:

(set (mem QI (add disp8 (reg h-gr 14))) Ri)

execution unit(s):
- fr30-1: u-store

str14h - sth Ri,@(R14,disp9)

machines: base

syntax: sth $Ri,@($R14,$disp9)

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-disp9 f-Ri

0x5 disp9 Ri

semantics:

(set (mem HI (add disp9 (reg h-gr 14))) Ri)

execution unit(s):
- fr30-1: u-store

str15 - st Ri,@(R15,udisp6) reg/mem

machines: base

syntax: st $Ri,@($R15,$udisp6)

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-udisp6 f-Ri

0x1 0x3 udisp6 Ri

semantics:

(set (mem WI (add (reg h-gr 15) udisp6)) Ri)

execution unit(s):
- fr30-1: u-store

str15dr - st Rs,@-R15 reg/mem

machines: base

syntax: st $Rs2,@-$R15

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-Rs2

0x1 0x7 0x8 Rs2

semantics:

(sequence
  ((WI tmp))
  (set tmp Rs2)
  (set (reg h-gr 15) (sub (reg h-gr 15) 4))
  (set (mem WI (reg h-gr 15)) tmp))

execution unit(s):
- fr30-1: u-store

str15gr - st Ri,@-R15 reg/mem

machines: base

syntax: st $Ri,@-$R15

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-Ri

0x1 0x7 0x0 Ri

semantics:

(sequence
  ((WI tmp))
  (set tmp Ri)
  (set (reg h-gr 15) (sub (reg h-gr 15) 4))
  (set (mem WI (reg h-gr 15)) tmp))

execution unit(s):
- fr30-1: u-store

str15ps - st ps,@-R15 reg/mem

machines: base

syntax: st $ps,@-$R15

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-op3 f-op4

0x1 0x7 0x9 0x0

semantics:

(sequence
  ()
  (set (reg h-gr 15) (sub (reg h-gr 15) 4))
  (set (mem WI (reg h-gr 15)) ps))

execution unit(s):
- fr30-1: u-store

stres - stres #u4,@Ri+

machines: base

syntax: stres $u4,@$Ri+

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-u4 f-Ri

0xb 0xd u4 Ri

semantics:
```
(set Ri (add Ri 4))
```

sub - sub reg/reg

machines: base

syntax: sub $Rj,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0xa 0xc Rj Ri

semantics:

(sequence
  ()
  (set vbit (sub-oflag Ri Rj 0))
  (set cbit (sub-cflag Ri Rj 0))
  (set Ri (sub Ri Rj))
  (sequence
    ()
    (set zbit (eq Ri 0))
    (set nbit (lt Ri 0))))

subc - subc reg/reg

machines: base

syntax: subc $Rj,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0xa 0xd Rj Ri

semantics:

(sequence
  ((WI tmp))
  (set tmp (subc Ri Rj cbit))
  (set vbit (sub-oflag Ri Rj cbit))
  (set cbit (sub-cflag Ri Rj cbit))
  (set Ri tmp)
  (sequence
    ()
    (set zbit (eq Ri 0))
    (set nbit (lt Ri 0))))

subn - subn reg/reg

machines: base

syntax: subn $Rj,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0xa 0xe Rj Ri

semantics:
```
(set Ri (sub Ri Rj))
```

xchb - xchb @Rj,Ri

machines: base

syntax: xchb @$Rj,$Ri

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rj f-Ri

0x8 0xa Rj Ri

semantics:

(sequence
  ((WI tmp))
  (set tmp Ri)
  (set Ri (mem UQI Rj))
  (set (mem UQI Rj) tmp))

execution unit(s):
- fr30-1: u-load u-store

Macro Instructions

Macro instructions for each machine:

fr30 - Generic FR30 cpu

Individual macro-instructions descriptions

ldi20m - ldi:20 without the colon

syntax: ldi20 $i20,$Ri

transformation:
```
((emit ldi20 i20 Ri))
```

ldi32m - ldi:32 without the colon

syntax: ldi32 $i32,$Ri

transformation:
```
((emit ldi32 i32 Ri))
```

ldi8m - ldi:8 without the colon

syntax: ldi8 $i8,$Ri

transformation:
```
((emit ldi8 i8 Ri))
```

This documentation was machine generated from the cgen cpu description files for this architecture.
http://sources.redhat.com/cgen/

0 1 2 3	4 5 6 7	8 9 10 11	12 13 14 15
f-op1	f-op2	f-Rj	f-Ri
0xa	0x6	Rj	Ri

0 1 2 3	4 5 6 7	8 9 10 11 12 13 14 15
f-op1	f-cc	f-rel9
0xe	0x4	label9

0 1 2 3	4	5 6 7 8 9 10 11 12 13 14 15
f-op1	f-op5	f-rel12
0xd	0x0	label12

0 1 2 3	4 5 6 7	8 9 10 11 12 13 14 15
f-op1	f-op2	f-s10
0xa	0x3	s10

Instructions

fr30 MEM - Memory

fr30 ALU - ALU

fr30 BR - Branch

fr30 fr30 - Generic FR30 cpu

Individual instructions descriptions

add - add reg/reg

add2 - add2 immed/reg

addc - addc reg/reg

addi - add immed/reg

addn - addn reg/reg

addn2 - addn2 immed/reg

addni - addn immed/reg

addsp - addsp #s10

and - and reg/reg

andb - andb reg/mem

andccr - andccr #u8

andh - andh reg/mem

andm - and reg/mem

asr - asr Rj,Ri

asr2 - asr2 u4,Ri

asri - asr u4,Ri

bandh - bandh #u4,@Ri

bandl - bandl #u4,@Ri

bc - bc label9

bcd - bc:d label9

beorh - beorh #u4,@args

beorl - beorl #u4,@Ri

beq - beq label9

beqd - beq:d label9

bge - bge label9

bged - bge:d label9

bgt - bgt label9

bgtd - bgt:d label9

bhi - bhi label9

bhid - bhi:d label9

ble - ble label9

bled - ble:d label9

bls - bls label9

blsd - bls:d label9

blt - blt label9

bltd - blt:d label9

bn - bn label9

bnc - bnc label9

bncd - bnc:d label9

bnd - bn:d label9

bne - bne label9

bned - bne:d label9

bno - bno label9

bnod - bno:d label9

bnv - bnv label9

bnvd - bnv:d label9

borh - borh #u4,@args

borl - borl #u4,@Ri

bp - bp label9

bpd - bp:d label9

bra - bra label9

brad - bra:d label9

btsth - btsth #u4,@Ri

btstl - btstl #u4,@Ri

bv - bv label9

bvd - bv:d label9

call - call relative to pc

calld - call relative to pc

callr - call @Ri

callrd - call:d @Ri

cmp - cmp reg/reg

cmp2 - cmp2 immed/reg

cmpi - cmp immed/reg

copld - copld u4c,ccc,CRj,Rjc,CRi

copop - copop u4c,ccc,CRj,CRj,CRi

copst - copst u4c,ccc,CRj,CRj,Ric

copsv - copsv u4c,ccc,CRj,CRj,Ric

div0s - div0s Ri

div0u - div0u Ri

div1 - div1 Ri

div2 - div2 Ri

div3 - div3

div4s - div4s

dmov2r13 - dmov @dir10,R13