ARM Architecture Documentation
DISCLAIMER: This documentation is derived from the cgen cpu description
of this architecture, and does not represent official documentation
of the chip maker.
In cgen-parlance, an architecture consists of machines and models.
A `machine' is the specification of a variant of the architecture,
and a `model' is the implementation of that specification.
Typically there is a one-to-one correspondance between machine and model.
The distinction allows for separation of what application programs see
(the machine), and how to tune for the chip (what the compiler sees).
A "cpu family" is a cgen concoction to help organize the generated code.
Chip variants that are quite dissimilar can be treated separately by the
generated code even though they're both members of the same architecture.
ARM Architecture
This section describes various things about the cgen description of
the ARM architecture. Familiarity with cgen cpu descriptions
is assumed.
Bit number orientation (arch.lsb0?): lsb = 0
ISA description
-
arm - ARM instruction set (32 bit insns)
- default-insn-word-bitsize: 32
- default-insn-bitsize: 32
- base-insn-bitsize: 32
- decode-assist: 27 26 25 24 23 22 21
- decode-splits:
- condition-field: f-cond
- condition:
(c-call BI "eval_cond" cond-code pc)
- setup-semantics:
((reg h-gr 15)
(add pc (attr (current-insn) R15-OFFSET)))
-
thumb - ARM Thumb instruction set (16 bit insns)
- default-insn-word-bitsize: 16
- default-insn-bitsize: 16
- base-insn-bitsize: 16
- decode-assist: 15 14 13 12 11 10 9 8
- decode-splits:
- setup-semantics:
((reg h-gr 15) (add pc 4))
CPU Families
-
arm7f - ARM7
Machines:
-
arm7tdmi - ARM 7TDMI core
Models:
-
arm710 - ARM 710 microprocessor
Machine variants
arm7tdmi - ARM 7TDMI core
-
bfd-name: arm7tdmi
-
isas: arm thumb
Model variants
arm710 - ARM 710 microprocessor
Registers
h-cbit - carry bit
-
machines: base
-
bitsize: 1
h-cpsr - Current Program Status Register
-
machines: base
-
bitsize: 32
h-fbit - fiq disable bit
-
machines: base
-
bitsize: 1
h-gr - General purpose registers
-
machines: base
-
bitsize: 32
-
array: [16]
names:
| pc |
15 |
| r0 |
0 |
| r1 |
1 |
| r2 |
2 |
| r3 |
3 |
| r4 |
4 |
| r5 |
5 |
| r6 |
6 |
| r7 |
7 |
| r8 |
8 |
| r9 |
9 |
| r10 |
10 |
| r11 |
11 |
| r12 |
12 |
| r13 |
13 |
| r14 |
14 |
| r15 |
15 |
| sp |
13 |
| lr |
14 |
h-gr-abt - abort mode r13-r14 regs
-
machines: base
-
bitsize: 32
-
array: [2]
h-gr-fiq - fiq mode r8-r14 regs
-
machines: base
-
bitsize: 32
-
array: [7]
h-gr-irq - irq mode r13-r14 regs
-
machines: base
-
bitsize: 32
-
array: [2]
h-gr-svc - supervisor mode r13-r14 regs
-
machines: base
-
bitsize: 32
-
array: [2]
h-gr-und - undefined mode r13-r14 regs
-
machines: base
-
bitsize: 32
-
array: [2]
h-gr-usr - user/system mode r8-r14 holding buffer
-
machines: base
-
bitsize: 32
-
array: [7]
h-ibit - irq disable bit
-
machines: base
-
bitsize: 1
h-mbits - m4,m3,m2,m1,m0
-
machines: base
-
bitsize: 5
h-nbit - negative bit
-
machines: base
-
bitsize: 1
h-pc - ARM program counter (h-gr reg 15)
-
machines: base
-
bitsize: 32
h-spsr - virtual spsr
-
machines: base
-
bitsize: 32
h-spsr-abt - Saved Process Status Register during Abort
-
machines: base
-
bitsize: 32
h-spsr-fiq - Saved Process Status Register during FIQ
-
machines: base
-
bitsize: 32
h-spsr-irq - Saved Process Status Register during IRQ
-
machines: base
-
bitsize: 32
h-spsr-svc - Saved Process Status Register during SVC
-
machines: base
-
bitsize: 32
h-spsr-und - Saved Process Status Register during Undefined
-
machines: base
-
bitsize: 32
h-tbit - thumb bit
-
machines: base
-
bitsize: 1
h-vbit - overflow bit
-
machines: base
-
bitsize: 1
h-zbit - zerobit
-
machines: base
-
bitsize: 1
Assembler supplemental
This documentation was machine generated from the cgen cpu description
files for this architecture.
http://sources.redhat.com/cgen/