hw-uart-ns16550 (libuart.la :: uart_component_library)


The PC16550D contains independent serial input and output ports that perform byte-at-a-time I/O. The 16550 is distinguished from its predecessor, the 16450, by two 16-byte FIFOs. The FIFOs allow the CPU to buffer data to reduce the frequency of interrupts. The 16550 also supports model-control functions DMA hand-shaking, and have a loop-back mode for testing.



The Uart model is somewhat abstracted from its hardware counterpart:

SID Conventions
functional supported -
save/restore supported -
reentrantnot supported -
target view manager supported

Pins and registers are both accessible from the Target View Manager


Related components

Component Reference:

Component: hw-uart-ns16550

Sinindata + parityserial input
Soutoutdata + parityserial output
INTRout0,1active high interrupt pin
TxRdyout0,1active low transmitter ready (dma control)
RxRdyout0,1active low receiver ready (dma control)
RTSout0,1active low request to send (modem control)
DTRout0,1active low data transmit ready (modem control)
OUT1out0,1active low user output (modem control)
OUT2out0,1active low user output (modem control)
CTSin0,1active low clear to send (modem control)
DSRin0,1active low data set ready (modem control)
RIin0,1active low ring indicator (modem control
DCDin0,1active low data carrier detect (modem control)
Resetinanymaster reset

Bus0x0-0x7read/write, bytes onlyaccess to registers

namecategorylegal valuesdefault valuebehaviors
timeoutwritepositive integers10sets the time to wait


National Semiconductor PC16550 data sheet, dated June 1995. This page has links to the data sheet and application notes (in PDF)