hw-timer-arm/ref (libtimers.la :: timer_component_library)


The timer peripheral on the ARM PID7T is a simple 16-bit down counter. It can be programmed with a number of modes and pre-scale values. For example, you can program the timer to raise an interrupt when a specified interval has elapsed. More details on the timer can be found in the ARM documentation (see ``References'').



This component models the ARM reference timer found on the ARM PID7T development board. The ARM PID7T comes with two such timers, which may or may not be implemented on the same piece of silicon. Instead of implementing a dual timer, you can configure a functionally equivalent system by using two instances of a single timer. This simplifies the implementation and provides more design flexibility to system builders.


Upon construction, or when the reset input pin is driven, the timer is reset to a powerup state. This includes deasserting the interrupt line and disabling counting.


The two variants of the ARM reference timer, hw-timer-arm/ref-sched and hw-timer-arm/ref-nosched, differ in the way that they receive clocking signals. The 'nosched' variant relies on a clock pin, which is interpreted as the regular "system clock". The `sched' variant relies on an external scheduler component to provide a pre-divided clock. Its divided-clock-control and divided-clock-event pins are used to signal to and from the scheduler.


Whenever the counter underflows, an interrupt signal is transmitted by driving the interrupt output pin to a nonzero value. When the interrupt is cleared, the pin is driven with a zero value.

register access

The registers bus provides access to a bank of control registers. The memory map, described in detail in the reference documentation, is as follows:

address read write
0 TimerLoad TimerLoad
4 TimerValue Reserved
8 TimerControl TimerControl
12 Reserved TimerClear
16 Reserved Reserved

SID Conventions
functional supported -
save/restore supported -
triggerpoints supported

The component supports triggerpoints set on any of the available attributes.


Related components

Host system

The hw-timer-arm/ref-sched variant of the timer is more efficient as it does not rely on yielding simulation time to the timer for every clock cycle; it should be used in almost all circumstances.

Component Reference:

Component: hw-timer-arm/ref (Abstract)

interruptout0 or non-zerointerrupting
divided-clock-controloutpositive valueclocking

registers0x0 to 0x13read/writeregister access

namecategorylegal valuesdefault valuebehaviors
counterwatchable registernumberregister access
load-valuewatchable registernumberregister access
enabledwatchable registertrue or falseregister access
modewatchable register`periodic' or `free-running'register access
prescalewatchable register0..3register access
tickswatchable register0..prescale-1clocking

Variant: hw-timer-arm/ref-sched

Same as hw-timer-arm/ref

Variant: hw-timer-arm/ref-nosched

Same as hw-timer-arm/ref


ARM reference documentation can be found on the web.