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Re: Misaligned read/write of memory by GDB
Frank Ch. Eigler wrote:
I thought about the possibility of fixing existing memory targets to
handle misaligned access, either by implementing support, returning
sid::bus::misaligned, or whatever else might be appropriate.
How many offenders (that did neither) did you encounter?
Just one. The cache component. It silently reads directly from the
backing memory, thus (potentially) returning the wrong value.
However it occurred to me that this would require implementors of all
future memory targets to be aware of potential GDB access of this
type. [...]
True, except that such accesses could originate elsewhere - a simulated
CPU, or a gloss component, for example.
I guess one could argue that all complete component implementations
should handle all possible input possibilities. The failure was not
obvious in my case because of the silent misbehavior of the cache
component. I guess I was just wanting to prevent a similar misfortune
from happening to someone else (or me again!) in the future.
Your gloss example convinces me that the cache component should be
fixed, however. Once done, I can implement the GDB access in the way
you've suggested.
Dave