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[patch][rfa] Improve cgen profile modelling for VLIW
- From: Dave Brolley <brolley at redhat dot com>
- To: sid at sources dot redhat dot com
- Date: Tue, 21 Oct 2003 13:49:45 -0400
- Subject: [patch][rfa] Improve cgen profile modelling for VLIW
- Organization: Red Hat Canada, Ltd
Hi,
This patch expands the recently-added cgen model support for cgen-cpu to
handle generic VLIW issues. It accumulates the maximum number of cycles
used by all insns in a VLIW bundle and then calls a virtual function
(step_latency) to allow the cpu to account for those cycles.
Tested against our internal port but generally useful for other
architectures.
ok to commit?
Dave
2003-10-07 Dave Brolley <brolley@redhat.com>
* cgen-model.h (class cgen_model): step_cycles and step_latency
now public.
2003-10-07 Dave Brolley <brolley@redhat.com>
* cgen-model.h (sidtypes.h): #include it.
(model_insn_before): Call step_latency. Initialize vliw_cycles.
(model_insn_after): Call step_cycles. Update vliw_cycles.
(step_cycles): New method.
(step_latency): New method.
(vliw_cycles): New member of cgen_model.
* cgen-engine.h (enum sem_status): Add SEM_STATUS_STALLED.
Index: sid/component/cgen-cpu/cgen-engine.h
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/cgen-engine.h,v
retrieving revision 1.4
diff -c -p -r1.4 cgen-engine.h
*** sid/component/cgen-cpu/cgen-engine.h 6 Feb 2003 20:44:34 -0000 1.4
--- sid/component/cgen-cpu/cgen-engine.h 21 Oct 2003 17:21:28 -0000
***************
*** 1,6 ****
// cgen-engine.h - CGEN engine support. -*- C++ -*-
! // Copyright (C) 1999, 2000 Red Hat.
// This file is part of SID and is licensed under the GPL.
// See the file COPYING.SID for conditions for redistribution.
--- 1,6 ----
// cgen-engine.h - CGEN engine support. -*- C++ -*-
! // Copyright (C) 1999, 2000, 2003 Red Hat.
// This file is part of SID and is licensed under the GPL.
// See the file COPYING.SID for conditions for redistribution.
*************** enum sem_status
*** 15,21 ****
{
SEM_STATUS_NORMAL,
SEM_STATUS_BRANCH_TAKEN,
! SEM_STATUS_DELAYED_BRANCH_TAKEN
};
// Exceptions used to exit the cpu's "main loop".
--- 15,22 ----
{
SEM_STATUS_NORMAL,
SEM_STATUS_BRANCH_TAKEN,
! SEM_STATUS_DELAYED_BRANCH_TAKEN,
! SEM_STATUS_STALLED
};
// Exceptions used to exit the cpu's "main loop".
Index: sid/component/cgen-cpu/cgen-model.h
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/cgen-model.h,v
retrieving revision 1.1
diff -c -p -r1.1 cgen-model.h
*** sid/component/cgen-cpu/cgen-model.h 16 Apr 2003 18:13:51 -0000 1.1
--- sid/component/cgen-cpu/cgen-model.h 21 Oct 2003 17:21:28 -0000
***************
*** 7,12 ****
--- 7,13 ----
#ifndef CGEN_MODEL_H
#define CGEN_MODEL_H
+ #include <sidtypes.h>
#include "cgen-cpu.h"
namespace cgen
*************** public:
*** 19,37 ****
// To be overridden as needed. Call before each insn is executed. first_p is
// true when the insn is the first of a group of parallel insns.
! virtual void model_insn_before (bool first_p = true) {}
// To be overridden as needed. Call after each insn is executed. last_p is
// true when the insn is the first of a group of parallel insns. cycles is the
// number of cycles used by each particular insn.
virtual void model_insn_after (bool last_p = true, sid::host_int_4 cycles = 1)
{
! if (last_p && cycles > 0)
cpu->update_total_latency (cycles - 1);
}
protected:
cgen_bi_endian_cpu *cpu;
};
} // namespace cgen
--- 20,69 ----
// To be overridden as needed. Call before each insn is executed. first_p is
// true when the insn is the first of a group of parallel insns.
! virtual void model_insn_before (bool first_p = true)
! {
! if (first_p)
! {
! // There may be latency from insn fetch.
! step_latency ();
! this->vliw_cycles = 1;
! }
! }
// To be overridden as needed. Call after each insn is executed. last_p is
// true when the insn is the first of a group of parallel insns. cycles is the
// number of cycles used by each particular insn.
virtual void model_insn_after (bool last_p = true, sid::host_int_4 cycles = 1)
{
! // Accumulate the max cycles used by any one vliw insn.
! if (cycles > this->vliw_cycles)
! this->vliw_cycles = cycles;
!
! // Account for the latency of this group of insns.
! if (last_p)
! step_cycles (vliw_cycles);
! }
!
! // To be overridden as needed. Update any state associated with an
! // insn using the given number of cycles.
! virtual void step_cycles (sid::host_int_4 cycles)
! {
! if (cycles > 0)
! {
! // The cpu counts cycles as number of insns + total latency.
cpu->update_total_latency (cycles - 1);
+ step_latency (1);
}
+ }
+
+ // To be overridden as needed. Update any state associated with an
+ // insn having latency. Insn latency is tracked using the cpu's
+ // get_total_latency () method.
+ virtual void step_latency (sid::host_int_4 = 0) {}
protected:
cgen_bi_endian_cpu *cpu;
+ sid::host_int_4 vliw_cycles;
};
} // namespace cgen