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[PATCH] Fix libgloss initialisation for MIPS


Hello All,

the appended patch fixes libgloss' crt0.S initialization of the
mips status register.


Thiemo


2006-11-06  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>

	* mips/crt0.S (_start): Use all available float registers. Don't touch
	SR_PE on post-mips2 CPUs, it means soft reset there.


Index: libgloss/mips/crt0.S
===================================================================
RCS file: /cvs/src/src/libgloss/mips/crt0.S,v
retrieving revision 1.9
diff -u -p -r1.9 crt0.S
--- libgloss/mips/crt0.S	26 May 2003 20:22:16 -0000	1.9
+++ libgloss/mips/crt0.S	6 Nov 2006 13:23:26 -0000
@@ -65,11 +65,21 @@ _start:
 	nop
 	move	s0,$31
 #endif
-#if !defined(__mips64) || (__mips_fpr==32)
-#define STATUS_MASK (SR_CU1|SR_PE)
+#if __mips<3
+#  define STATUS_MASK (SR_CU1|SR_PE)
 #else
-# For mips3 or mips4, turn on 64-bit addressing and additional float regs
-#define STATUS_MASK (SR_CU1|SR_PE|SR_FR|SR_KX|SR_SX|SR_UX)
+/* Post-mips2 has no SR_PE bit.  */
+#  ifdef __mips64
+/* Turn on 64-bit addressing and additional float regs.  */
+#    define STATUS_MASK (SR_CU1|SR_FR|SR_KX|SR_SX|SR_UX)
+#  else
+#    ifdef __mips_fpr=32
+#      define STATUS_MASK (SR_CU1)
+#    else
+/* Turn on additional float regs.  */
+#      define STATUS_MASK (SR_CU1|SR_FR)
+#    endif
+#  endif
 #endif
 	li	v0, STATUS_MASK
 	mtc0	v0, C0_SR


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