RISC-V port

["Stefan O'Rear" <sorear2 at gmail dot com>]

I have a [libffi
patch](https://github.com/sorear/libffi-riscv/commit/e9639dc79.diff)
which adds support for the RISC-V architecture.

*I did not write* the code in this patch; it is a cleaned up and
rebased version of a [port](https://github.com/riscv/riscv-libffi) by
Michael Knyszek et al of UC Berkeley.

RISC-V is a free and open standard instruction set architecture
originally developed at UC Berkeley and now seeing significant
interest from independent hardware vendors, with interoperable
prototypes from several independent groups.  Alex Bradbury's [recent
RFC to the LLVM
community](http://lists.llvm.org/pipermail/llvm-dev/2016-August/103748.html)
has a much better explanation of what RISC-V is and why you should
care about it.

While the privileged architecture is still in some flux, the
architecture which is visible to user space and the C calling
convention have been unchanged in nearly two years and are now
considered frozen, so ports like this one are very likely to remain
valid.

I am interested in being the responsible party to get this code into a
mergable condition.  I am familiar with the RISC-V ISA and calling
convention and with libffi's broad principles of operation, but not
with the details of libffi internals.

How shall we proceed?

-s