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[PATCH ppc] memset to 0 is broken on PPC405/440/464


The use_dcbz path in the hand coded assembly is assuming a 128 byte
clear size for dcbz, but dcbz uses the cache line size and 405 cores
only have a 32 byte cache line. So any clears to 0 that use the dcbz
path fail to work.

This seems to be because the memset.S file was designed for the 476
CPU, which does have a 128 byte cache line size, however 405, 440, and
464 all use 32 bytes. (see arch/powerpc/kernel/cputable.c)

This patch corrects the 405 memset.s to have the correct 32 byte cache
size, but the 476 must continue to use the old version or it will
clear too much. Unfortunately I'm not entirely sure how to do that (eg
how does Implies work?)

See http://sourceware.org/bugzilla/show_bug.cgi?id=14595

Tested in-circuit on a 405GP CPU

--- eglibc-2_13.orig/ports/sysdeps/powerpc/powerpc32/405/memset.S	2012-09-18 23:06:38.743817536 -0600
+++ eglibc-2_13/ports/sysdeps/powerpc/powerpc32/405/memset.S	2012-09-18 23:09:48.677194920 -0600
@@ -105,7 +105,7 @@
        add     r3,r3,r7
 
 L(skip_string_loop):
-       clrlwi  r8,r6,25
+       clrlwi  r8,r6,27
        srwi.   r8,r8,4
        beq     L(dcbz_pre_loop)
        mtctr   r8
@@ -120,14 +120,14 @@
        bdnz    L(word_loop)
 
 L(dcbz_pre_loop):
-       srwi    r6,r5,7
+       srwi    r6,r5,5
        mtctr   r6
        addi    r7,0,0
 
 L(dcbz_loop):
        dcbz    r3,r7
-       addi    r3,r3,0x80
-       subi    r5,r5,0x80
+       addi    r3,r3,32
+       subi    r5,r5,32
        bdnz    L(dcbz_loop)
        srwi.   r6,r5,4
        beq     L(postword2_count_loop)


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