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Re: [PATCH 1/3, MIPS] Rewrite MIPS' atomic.h to use __atomic_* builtins.
On 15/06/2012, at 11:24 PM, Joseph S. Myers wrote:
> On Fri, 15 Jun 2012, Maxim Kuvyrkov wrote:
>
>> * sysdeps/mips/bit/atomic.h [__GNUC_PREREQ (4, 8)]
>
> Again, "bits" not "bit".
>
>> (__arch_compare_and_exchange_bool_acq_32_int,)
>
> No comma before the closing parenthesis on each line.
>
>> +#if __GNUC_PREREQ (4, 8)
>> +/* The __atomic_* builtins are available in GCC 4.7 and later, but MIPS
>> + support for their efficient implementation was added only in GCC 4.8. */
>> +
>> +/* Compare and exchange.
>> + For all "bool" routines, we return FALSE if exchange succesful. */
>> +
>> +#define __arch_compare_and_exchange_bool_acq_8_int(mem, newval, oldval) \
>> + (abort (), 0)
>
> "# define" inside #if (yes, this does mean adding spaces after the "#" for
> the existing definitions that are now conditional).
>
>> +/* This implementation using inline assembly will be removed once GLIBC
>> + requires GCC 4.8 or later to build. */
>
> glibc, not GLIBC (see
> <http://sourceware.org/ml/libc-alpha/2012-05/msg01944.html>).
>
> More review later.
Here is an updated patch fixed per above comments.
--
Maxim Kuvyrkov
CodeSourcery / Mentor Graphics
Rewrite MIPS' atomic.h to use __atomic_* builtins.
2012-06-14 Tom de Vries <vries@codesourcery.com>
Maxim Kuvyrkov <maxim@codesourcery.com>
* sysdeps/mips/bits/atomic.h [__GNUC_PREREQ (4, 8)]
(__arch_compare_and_exchange_bool_acq_32_int)
(__arch_compare_and_exchange_bool_rel_32_int)
(__arch_compare_and_exchange_val_acq_32_int)
(__arch_compare_and_exchange_val_rel_32_int)
(__arch_compare_and_exchange_bool_acq_64_int)
(__arch_compare_and_exchange_bool_rel_64_int)
(__arch_compare_and_exchange_val_acq_64_int)
(__arch_compare_and_exchange_val_rel_64_int):
Define in terms of __atomic_compare_exchange_n.
[__GNUC_PREREQ (4, 8)]
(__arch_exchange_acq_32_int, __arch_exchange_rel_32_int)
(__arch_exchange_acq_64_int, __arch_exchange_rel_64_int):
Define in terms of __atomic_exchange_n.
[__GNUC_PREREQ (4, 8)]
(__arch_fetch_and_add_32_int, __arch_fetch_and_add_64_int):
Define in terms of __atomic_fetch_add.
[!__GNUC_PREREQ (4, 8)]: Update formatting.
---
sysdeps/mips/bits/atomic.h | 257 +++++++++++++++++++++++++++++++++++++-------
1 files changed, 217 insertions(+), 40 deletions(-)
diff --git a/sysdeps/mips/bits/atomic.h b/sysdeps/mips/bits/atomic.h
index 4d51d7f..9038624 100644
--- a/sysdeps/mips/bits/atomic.h
+++ b/sysdeps/mips/bits/atomic.h
@@ -1,5 +1,5 @@
/* Low-level functions for atomic operations. Mips version.
- Copyright (C) 2005 Free Software Foundation, Inc.
+ Copyright (C) 2005-2012 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
@@ -78,17 +78,193 @@ typedef uintmax_t uatomic_max_t;
#define MIPS_SYNC_STR_1(X) MIPS_SYNC_STR_2(X)
#define MIPS_SYNC_STR MIPS_SYNC_STR_1(MIPS_SYNC)
+#if __GNUC_PREREQ (4, 8)
+/* The __atomic_* builtins are available in GCC 4.7 and later, but MIPS
+ support for their efficient implementation was added only in GCC 4.8. */
+
+/* Compare and exchange.
+ For all "bool" routines, we return FALSE if exchange succesful. */
+
+# define __arch_compare_and_exchange_bool_acq_8_int(mem, newval, oldval) \
+ (abort (), 0)
+
+# define __arch_compare_and_exchange_bool_rel_8_int(mem, newval, oldval) \
+ (abort (), 0)
+
+# define __arch_compare_and_exchange_bool_acq_16_int(mem, newval, oldval) \
+ (abort (), 0)
+
+# define __arch_compare_and_exchange_bool_rel_16_int(mem, newval, oldval) \
+ (abort (), 0)
+
+# define __arch_compare_and_exchange_bool_acq_32_int(mem, newval, oldval) \
+ ({ \
+ typeof (*mem) __oldval = (oldval); \
+ !__atomic_compare_exchange_n (mem, &__oldval, newval, 0, \
+ __ATOMIC_ACQUIRE, __ATOMIC_RELAXED); \
+ })
+
+# define __arch_compare_and_exchange_bool_rel_32_int(mem, newval, oldval) \
+ ({ \
+ typeof (*mem) __oldval = (oldval); \
+ !__atomic_compare_exchange_n (mem, &__oldval, newval, 0, \
+ __ATOMIC_RELEASE, __ATOMIC_RELAXED); \
+ })
+
+# define __arch_compare_and_exchange_val_acq_8_int(mem, newval, oldval) \
+ (abort (), 0)
+
+# define __arch_compare_and_exchange_val_rel_8_int(mem, newval, oldval) \
+ (abort (), 0)
+
+# define __arch_compare_and_exchange_val_acq_16_int(mem, newval, oldval) \
+ (abort (), 0)
+
+# define __arch_compare_and_exchange_val_rel_16_int(mem, newval, oldval) \
+ (abort (), 0)
+
+# define __arch_compare_and_exchange_val_acq_32_int(mem, newval, oldval) \
+ ({ \
+ typeof (*mem) __oldval = (oldval); \
+ __atomic_compare_exchange_n (mem, &__oldval, newval, 0, \
+ __ATOMIC_ACQUIRE, __ATOMIC_RELAXED); \
+ __oldval; \
+ })
+
+# define __arch_compare_and_exchange_val_rel_32_int(mem, newval, oldval) \
+ ({ \
+ typeof (*mem) __oldval = (oldval); \
+ __atomic_compare_exchange_n (mem, &__oldval, newval, 0, \
+ __ATOMIC_RELEASE, __ATOMIC_RELAXED); \
+ __oldval; \
+ })
+
+# if _MIPS_SIM == _ABIO32
+ /* We can't do an atomic 64-bit operation in O32. */
+# define __arch_compare_and_exchange_bool_acq_64_int(mem, newval, oldval) \
+ (abort (), 0)
+# define __arch_compare_and_exchange_bool_rel_64_int(mem, newval, oldval) \
+ (abort (), 0)
+# define __arch_compare_and_exchange_val_acq_64_int(mem, newval, oldval) \
+ (abort (), 0)
+# define __arch_compare_and_exchange_val_rel_64_int(mem, newval, oldval) \
+ (abort (), 0)
+# else
+# define __arch_compare_and_exchange_bool_acq_64_int(mem, newval, oldval) \
+ __arch_compare_and_exchange_bool_acq_32_int (mem, newval, oldval)
+
+# define __arch_compare_and_exchange_bool_rel_64_int(mem, newval, oldval) \
+ __arch_compare_and_exchange_bool_rel_32_int (mem, newval, oldval)
+
+# define __arch_compare_and_exchange_val_acq_64_int(mem, newval, oldval) \
+ __arch_compare_and_exchange_val_acq_32_int (mem, newval, oldval)
+
+# define __arch_compare_and_exchange_val_rel_64_int(mem, newval, oldval) \
+ __arch_compare_and_exchange_val_rel_32_int (mem, newval, oldval)
+
+# endif
+
+/* Compare and exchange with "acquire" semantics, ie barrier after. */
+
+# define atomic_compare_and_exchange_bool_acq(mem, new, old) \
+ (__atomic_bool_bysize (__arch_compare_and_exchange_bool_acq, int, \
+ mem, new, old))
+
+# define atomic_compare_and_exchange_val_acq(mem, new, old) \
+ __atomic_val_bysize (__arch_compare_and_exchange_val_acq, int, \
+ mem, new, old)
+
+/* Compare and exchange with "release" semantics, ie barrier before. */
+
+# define atomic_compare_and_exchange_bool_rel(mem, new, old) \
+ (__atomic_bool_bysize (__arch_compare_and_exchange_bool_rel, int, \
+ mem, new, old))
+
+# define atomic_compare_and_exchange_val_rel(mem, new, old) \
+ __atomic_val_bysize (__arch_compare_and_exchange_val_rel, int, \
+ mem, new, old)
+
+
+/* Atomic exchange (without compare). */
+
+# define __arch_exchange_acq_8_int(mem, newval) \
+ (abort (), 0)
+
+# define __arch_exchange_rel_8_int(mem, newval) \
+ (abort (), 0)
+
+# define __arch_exchange_acq_16_int(mem, newval) \
+ (abort (), 0)
+
+# define __arch_exchange_rel_16_int(mem, newval) \
+ (abort (), 0)
+
+# define __arch_exchange_acq_32_int(mem, newval) \
+ __atomic_exchange_n (mem, newval, __ATOMIC_ACQUIRE)
+
+# define __arch_exchange_rel_32_int(mem, newval) \
+ __atomic_exchange_n (mem, newval, __ATOMIC_RELEASE)
+
+# if _MIPS_SIM == _ABIO32
+/* We can't do an atomic 64-bit operation in O32. */
+# define __arch_exchange_acq_64_int(mem, newval) \
+ (abort (), 0)
+# define __arch_exchange_rel_64_int(mem, newval) \
+ (abort (), 0)
+# else
+# define __arch_exchange_acq_64_int(mem, newval) \
+ __atomic_exchange_n (mem, newval, __ATOMIC_ACQUIRE)
+
+# define __arch_exchange_rel_64_int(mem, newval) \
+ __atomic_exchange_n (mem, newval, __ATOMIC_RELEASE)
+# endif
+
+# define atomic_exchange_acq(mem, value) \
+ __atomic_val_bysize (__arch_exchange_acq, int, mem, value)
+
+# define atomic_exchange_rel(mem, value) \
+ __atomic_val_bysize (__arch_exchange_rel, int, mem, value)
+
+
+/* Atomically add value and return the previous (unincremented) value. */
+
+# define __arch_exchange_and_add_8_int(mem, newval) \
+ (abort (), (typeof(*mem)) 0)
+
+# define __arch_exchange_and_add_16_int(mem, newval) \
+ (abort (), (typeof(*mem)) 0)
+
+# define __arch_exchange_and_add_32_int(mem, value) \
+ __atomic_fetch_add (mem, value, __ATOMIC_ACQ_REL)
+
+# if _MIPS_SIM == _ABIO32
+/* We can't do an atomic 64-bit operation in O32. */
+# define __arch_exchange_and_add_64_int(mem, value) \
+ (abort (), (typeof(*mem)) 0)
+# else
+# define __arch_exchange_and_add_64_int(mem, value) \
+ __atomic_fetch_add (mem, value, __ATOMIC_ACQ_REL)
+# endif
+
+/* ??? Barrier semantics for atomic_exchange_and_add appear to be
+ undefined. Use full barrier for now, as that's safe. */
+# define atomic_exchange_and_add(mem, value) \
+ __atomic_val_bysize (__arch_exchange_and_add, int, mem, value)
+#else /* !__GNUC_PREREQ (4, 8) */
+/* This implementation using inline assembly will be removed once glibc
+ requires GCC 4.8 or later to build. */
+
/* Compare and exchange. For all of the "xxx" routines, we expect a
"__prev" and a "__cmp" variable to be provided by the enclosing scope,
in which values are returned. */
-#define __arch_compare_and_exchange_xxx_8_int(mem, newval, oldval, rel, acq) \
+# define __arch_compare_and_exchange_xxx_8_int(mem, newval, oldval, rel, acq) \
(abort (), __prev = __cmp = 0)
-#define __arch_compare_and_exchange_xxx_16_int(mem, newval, oldval, rel, acq) \
+# define __arch_compare_and_exchange_xxx_16_int(mem, newval, oldval, rel, acq) \
(abort (), __prev = __cmp = 0)
-#define __arch_compare_and_exchange_xxx_32_int(mem, newval, oldval, rel, acq) \
+# define __arch_compare_and_exchange_xxx_32_int(mem, newval, oldval, rel, acq) \
__asm__ __volatile__ ( \
".set push\n\t" \
MIPS_PUSH_MIPS2 \
@@ -107,12 +283,12 @@ typedef uintmax_t uatomic_max_t;
: "r" (oldval), "r" (newval), "m" (*mem) \
: "memory")
-#if _MIPS_SIM == _ABIO32
+# if _MIPS_SIM == _ABIO32
/* We can't do an atomic 64-bit operation in O32. */
-#define __arch_compare_and_exchange_xxx_64_int(mem, newval, oldval, rel, acq) \
+# define __arch_compare_and_exchange_xxx_64_int(mem, newval, oldval, rel, acq) \
(abort (), __prev = __cmp = 0)
-#else
-#define __arch_compare_and_exchange_xxx_64_int(mem, newval, oldval, rel, acq) \
+# else
+# define __arch_compare_and_exchange_xxx_64_int(mem, newval, oldval, rel, acq) \
__asm__ __volatile__ ("\n" \
".set push\n\t" \
MIPS_PUSH_MIPS2 \
@@ -130,26 +306,26 @@ typedef uintmax_t uatomic_max_t;
: "=&r" (__prev), "=&r" (__cmp), "=m" (*mem) \
: "r" (oldval), "r" (newval), "m" (*mem) \
: "memory")
-#endif
+# endif
/* For all "bool" routines, we return FALSE if exchange succesful. */
-#define __arch_compare_and_exchange_bool_8_int(mem, new, old, rel, acq) \
+# define __arch_compare_and_exchange_bool_8_int(mem, new, old, rel, acq) \
({ typeof (*mem) __prev; int __cmp; \
__arch_compare_and_exchange_xxx_8_int(mem, new, old, rel, acq); \
!__cmp; })
-#define __arch_compare_and_exchange_bool_16_int(mem, new, old, rel, acq) \
+# define __arch_compare_and_exchange_bool_16_int(mem, new, old, rel, acq) \
({ typeof (*mem) __prev; int __cmp; \
__arch_compare_and_exchange_xxx_16_int(mem, new, old, rel, acq); \
!__cmp; })
-#define __arch_compare_and_exchange_bool_32_int(mem, new, old, rel, acq) \
+# define __arch_compare_and_exchange_bool_32_int(mem, new, old, rel, acq) \
({ typeof (*mem) __prev; int __cmp; \
__arch_compare_and_exchange_xxx_32_int(mem, new, old, rel, acq); \
!__cmp; })
-#define __arch_compare_and_exchange_bool_64_int(mem, new, old, rel, acq) \
+# define __arch_compare_and_exchange_bool_64_int(mem, new, old, rel, acq) \
({ typeof (*mem) __prev; int __cmp; \
__arch_compare_and_exchange_xxx_64_int(mem, new, old, rel, acq); \
!__cmp; })
@@ -157,43 +333,43 @@ typedef uintmax_t uatomic_max_t;
/* For all "val" routines, return the old value whether exchange
successful or not. */
-#define __arch_compare_and_exchange_val_8_int(mem, new, old, rel, acq) \
+# define __arch_compare_and_exchange_val_8_int(mem, new, old, rel, acq) \
({ typeof (*mem) __prev; int __cmp; \
__arch_compare_and_exchange_xxx_8_int(mem, new, old, rel, acq); \
(typeof (*mem))__prev; })
-#define __arch_compare_and_exchange_val_16_int(mem, new, old, rel, acq) \
+# define __arch_compare_and_exchange_val_16_int(mem, new, old, rel, acq) \
({ typeof (*mem) __prev; int __cmp; \
__arch_compare_and_exchange_xxx_16_int(mem, new, old, rel, acq); \
(typeof (*mem))__prev; })
-#define __arch_compare_and_exchange_val_32_int(mem, new, old, rel, acq) \
+# define __arch_compare_and_exchange_val_32_int(mem, new, old, rel, acq) \
({ typeof (*mem) __prev; int __cmp; \
__arch_compare_and_exchange_xxx_32_int(mem, new, old, rel, acq); \
(typeof (*mem))__prev; })
-#define __arch_compare_and_exchange_val_64_int(mem, new, old, rel, acq) \
+# define __arch_compare_and_exchange_val_64_int(mem, new, old, rel, acq) \
({ typeof (*mem) __prev; int __cmp; \
__arch_compare_and_exchange_xxx_64_int(mem, new, old, rel, acq); \
(typeof (*mem))__prev; })
/* Compare and exchange with "acquire" semantics, ie barrier after. */
-#define atomic_compare_and_exchange_bool_acq(mem, new, old) \
+# define atomic_compare_and_exchange_bool_acq(mem, new, old) \
__atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \
mem, new, old, "", MIPS_SYNC_STR)
-#define atomic_compare_and_exchange_val_acq(mem, new, old) \
+# define atomic_compare_and_exchange_val_acq(mem, new, old) \
__atomic_val_bysize (__arch_compare_and_exchange_val, int, \
mem, new, old, "", MIPS_SYNC_STR)
/* Compare and exchange with "release" semantics, ie barrier before. */
-#define atomic_compare_and_exchange_bool_rel(mem, new, old) \
+# define atomic_compare_and_exchange_bool_rel(mem, new, old) \
__atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \
mem, new, old, MIPS_SYNC_STR, "")
-#define atomic_compare_and_exchange_val_rel(mem, new, old) \
+# define atomic_compare_and_exchange_val_rel(mem, new, old) \
__atomic_val_bysize (__arch_compare_and_exchange_val, int, \
mem, new, old, MIPS_SYNC_STR, "")
@@ -201,13 +377,13 @@ typedef uintmax_t uatomic_max_t;
/* Atomic exchange (without compare). */
-#define __arch_exchange_xxx_8_int(mem, newval, rel, acq) \
+# define __arch_exchange_xxx_8_int(mem, newval, rel, acq) \
(abort (), 0)
-#define __arch_exchange_xxx_16_int(mem, newval, rel, acq) \
+# define __arch_exchange_xxx_16_int(mem, newval, rel, acq) \
(abort (), 0)
-#define __arch_exchange_xxx_32_int(mem, newval, rel, acq) \
+# define __arch_exchange_xxx_32_int(mem, newval, rel, acq) \
({ typeof (*mem) __prev; int __cmp; \
__asm__ __volatile__ ("\n" \
".set push\n\t" \
@@ -226,12 +402,12 @@ typedef uintmax_t uatomic_max_t;
: "memory"); \
__prev; })
-#if _MIPS_SIM == _ABIO32
+# if _MIPS_SIM == _ABIO32
/* We can't do an atomic 64-bit operation in O32. */
-#define __arch_exchange_xxx_64_int(mem, newval, rel, acq) \
+# define __arch_exchange_xxx_64_int(mem, newval, rel, acq) \
(abort (), 0)
-#else
-#define __arch_exchange_xxx_64_int(mem, newval, rel, acq) \
+# else
+# define __arch_exchange_xxx_64_int(mem, newval, rel, acq) \
({ typeof (*mem) __prev; int __cmp; \
__asm__ __volatile__ ("\n" \
".set push\n\t" \
@@ -249,24 +425,24 @@ typedef uintmax_t uatomic_max_t;
: "r" (newval), "m" (*mem) \
: "memory"); \
__prev; })
-#endif
+# endif
-#define atomic_exchange_acq(mem, value) \
+# define atomic_exchange_acq(mem, value) \
__atomic_val_bysize (__arch_exchange_xxx, int, mem, value, "", MIPS_SYNC_STR)
-#define atomic_exchange_rel(mem, value) \
+# define atomic_exchange_rel(mem, value) \
__atomic_val_bysize (__arch_exchange_xxx, int, mem, value, MIPS_SYNC_STR, "")
/* Atomically add value and return the previous (unincremented) value. */
-#define __arch_exchange_and_add_8_int(mem, newval, rel, acq) \
+# define __arch_exchange_and_add_8_int(mem, newval, rel, acq) \
(abort (), (typeof(*mem)) 0)
-#define __arch_exchange_and_add_16_int(mem, newval, rel, acq) \
+# define __arch_exchange_and_add_16_int(mem, newval, rel, acq) \
(abort (), (typeof(*mem)) 0)
-#define __arch_exchange_and_add_32_int(mem, value, rel, acq) \
+# define __arch_exchange_and_add_32_int(mem, value, rel, acq) \
({ typeof (*mem) __prev; int __cmp; \
__asm__ __volatile__ ("\n" \
".set push\n\t" \
@@ -285,12 +461,12 @@ typedef uintmax_t uatomic_max_t;
: "memory"); \
__prev; })
-#if _MIPS_SIM == _ABIO32
+# if _MIPS_SIM == _ABIO32
/* We can't do an atomic 64-bit operation in O32. */
-#define __arch_exchange_and_add_64_int(mem, value, rel, acq) \
+# define __arch_exchange_and_add_64_int(mem, value, rel, acq) \
(abort (), (typeof(*mem)) 0)
-#else
-#define __arch_exchange_and_add_64_int(mem, value, rel, acq) \
+# else
+# define __arch_exchange_and_add_64_int(mem, value, rel, acq) \
({ typeof (*mem) __prev; int __cmp; \
__asm__ __volatile__ ( \
".set push\n\t" \
@@ -308,13 +484,14 @@ typedef uintmax_t uatomic_max_t;
: "r" (value), "m" (*mem) \
: "memory"); \
__prev; })
-#endif
+# endif
/* ??? Barrier semantics for atomic_exchange_and_add appear to be
undefined. Use full barrier for now, as that's safe. */
-#define atomic_exchange_and_add(mem, value) \
+# define atomic_exchange_and_add(mem, value) \
__atomic_val_bysize (__arch_exchange_and_add, int, mem, value, \
MIPS_SYNC_STR, MIPS_SYNC_STR)
+#endif /* __GNUC_PREREQ (4, 8) */
/* TODO: More atomic operations could be implemented efficiently; only the
basic requirements are done. */
--
1.7.4.1