Re: [PATCH] powerpc: Use lwsync on 64bit

["Tulio Magno Quites Machado Filho" <tuliom at linux dot vnet dot ibm dot com>]

Adhemerval Zanella <adhemerval.zanella@linaro.org> writes:

> I do not think this is correct for all the primitives that use
> __ARCH_ACQ_INSTR.  For instance __arch_atomic_exchange_32_acq is defined as
>
> #define __arch_atomic_exchange_32_acq(mem, value)                             \
>   ({                                                                          \
>     __typeof (*mem) __val;                                                    \
>     __asm __volatile (                                                        \
>                       "1:       lwarx   %0,0,%2" MUTEX_HINT_ACQ "\n"          \
>                       "         stwcx.  %3,0,%2\n"                            \
>                       "         bne-    1b\n"                                 \
>                       "   " __ARCH_ACQ_INSTR                                  \
>                       : "=&r" (__val), "=m" (*mem)                            \
>                       : "b" (mem), "r" (value), "m" (*mem)                    \
>                       : "cr0", "memory");                                     \
>     __val;                                                                    \
>   })
>
>
> Which is analogous to C11:
>
> #include <stdatomic.h>
> #include <stdint.h>
>
> uint32_t foo (uint32_t *x)
> {
>   return atomic_exchange_explicit (x, 0, memory_order_acquire);
> }
>
> And GCC 6.2.1 uses and 'isync' a memory barrier.  It is also on par with [1]
> which defines acquire semantics to require 'isync' instructions.
>
>
> [1] https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html

Good point.
Per this document, it would also mess with the spinlock.

Anton, are you trying to fix a more specific issue?

-- 
Tulio Magno