This is the mail archive of the libc-alpha@sourceware.org mailing list for the glibc project.

Index Nav:	[Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav:	[Date Prev] [Date Next]	[Thread Prev] [Thread Next]
Other format:	[Raw text]

Re: [PING][PATCH][SPARC] supporting more than 2g in niagara4 memcpy and memset

From: jose dot marchesi at oracle dot com (Jose E. Marchesi)
To: David Miller <davem at davemloft dot net>
Cc: neleai at seznam dot cz, libc-alpha at sourceware dot org
Date: Wed, 28 Oct 2015 22:46:23 +0100
Subject: Re: [PING][PATCH][SPARC] supporting more than 2g in niagara4 memcpy and memset
Authentication-results: sourceware.org; auth=none
References: <20141111 dot 181731 dot 175723761716682896 dot davem at davemloft dot net> <87wq70svng dot fsf at oracle dot com> <20141127164710 dot GA13263 at domone> <20141127 dot 185030 dot 1164068896525820936 dot davem at davemloft dot net>

    > David, could you say if this fix is ok?
    
    It's not ok, it needs to either remove the conditional XCC
    stuff, or define something appropriate in the sparcv9 32-bit
    case.

This version of the patch defines XCC as icc in sparcv9.  Tested in
sparcv9-linux-gnu and sparc64-linux-gnu targets.  No regressions found.
   
2015-10-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
    
    	* sysdeps/sparc/sparc64/multiarch/memcpy-niagara4.S: Use the XCC
    	condition codes when comparing buffer sizes.
    	* sysdeps/sparc/sparc64/multiarch/memset-niagara4.S: Likewise.


diff --git a/sysdeps/sparc/sparc32/sparcv9/multiarch/memcpy-niagara4.S b/sysdeps/sparc/sparc32/sparcv9/multiarch/memcpy-niagara4.S
index 75ef9c0..0c00338 100644
--- a/sysdeps/sparc/sparc32/sparcv9/multiarch/memcpy-niagara4.S
+++ b/sysdeps/sparc/sparc32/sparcv9/multiarch/memcpy-niagara4.S
@@ -1 +1,2 @@
+#define XCC icc
 #include <sparc64/multiarch/memcpy-niagara4.S>
diff --git a/sysdeps/sparc/sparc32/sparcv9/multiarch/memset-niagara4.S b/sysdeps/sparc/sparc32/sparcv9/multiarch/memset-niagara4.S
index 6545019..c2ec2c4 100644
--- a/sysdeps/sparc/sparc32/sparcv9/multiarch/memset-niagara4.S
+++ b/sysdeps/sparc/sparc32/sparcv9/multiarch/memset-niagara4.S
@@ -1 +1,2 @@
+#define XCC icc
 #include <sparc64/multiarch/memset-niagara4.S>
diff --git a/sysdeps/sparc/sparc64/multiarch/memcpy-niagara4.S b/sysdeps/sparc/sparc64/multiarch/memcpy-niagara4.S
index ada7cf2..a00ec86 100644
--- a/sysdeps/sparc/sparc64/multiarch/memcpy-niagara4.S
+++ b/sysdeps/sparc/sparc64/multiarch/memcpy-niagara4.S
@@ -46,6 +46,11 @@
 #define STORE(type,src,addr)	type src, [addr]
 #define STORE_INIT(src,addr)	stxa src, [addr] STORE_ASI
 
+#ifndef XCC
+#define USE_BPR
+#define XCC xcc
+#endif
+	
 #if IS_IN (libc)
 
 	.register	%g2,#scratch
@@ -69,12 +74,12 @@ ENTRY(__memcpy_niagara4)
 #endif
 	brz,pn		%o2, .Lexit
 	 cmp		%o2, 3
-	ble,pn		%icc, .Ltiny
+	ble,pn		%XCC, .Ltiny
 	 cmp		%o2, 19
-	ble,pn		%icc, .Lsmall
+	ble,pn		%XCC, .Lsmall
 	 or		%o0, %o1, %g2
 	cmp		%o2, 128
-	bl,pn		%icc, .Lmedium
+	bl,pn		%XCC, .Lmedium
 	 nop
 
 .Llarge:/* len >= 0x80 */
@@ -152,14 +157,14 @@ ENTRY(__memcpy_niagara4)
 	add		%o0, 0x08, %o0
 	EX_ST(STORE_INIT(GLOBAL_SPARE, %o0))
 	add		%o0, 0x08, %o0
-	bne,pt		%icc, 1b
+	bne,pt		%XCC, 1b
 	 LOAD(prefetch, %o1 + 0x200, #n_reads_strong)
 
 	membar		#StoreLoad | #StoreStore
 
 	brz,pn		%o2, .Lexit
 	 cmp		%o2, 19
-	ble,pn		%icc, .Lsmall_unaligned
+	ble,pn		%XCC, .Lsmall_unaligned
 	 nop
 	ba,a,pt		%icc, .Lmedium_noprefetch
 
@@ -200,7 +205,7 @@ ENTRY(__memcpy_niagara4)
 	EX_ST(STORE(std, %f28, %o0 + 0x30))
 	EX_ST(STORE(std, %f30, %o0 + 0x38))
 	add		%o0, 0x40, %o0
-	bne,pt		%icc, 1b
+	bne,pt		%XCC, 1b
 	 LOAD(prefetch, %g1 + 0x200, #n_reads_strong)
 	VISExitHalf
 
diff --git a/sysdeps/sparc/sparc64/multiarch/memset-niagara4.S b/sysdeps/sparc/sparc64/multiarch/memset-niagara4.S
index 508997e..527f1f7 100644
--- a/sysdeps/sparc/sparc64/multiarch/memset-niagara4.S
+++ b/sysdeps/sparc/sparc64/multiarch/memset-niagara4.S
@@ -21,6 +21,11 @@
 
 #define ASI_BLK_INIT_QUAD_LDD_P	0xe2
 
+#ifndef XCC
+#define USE_BPR
+#define XCC xcc
+#endif
+	
 #if IS_IN (libc)
 
 	.register	%g2, #scratch
@@ -46,7 +51,7 @@ END(__memset_niagara4)
 ENTRY(__bzero_niagara4)
 	clr		%o4
 1:	cmp		%o1, 16
-	ble		%icc, .Ltiny
+	ble		%XCC, .Ltiny
 	 mov		%o0, %o3
 	sub		%g0, %o0, %g1
 	and		%g1, 0x7, %g1
@@ -58,7 +63,7 @@ ENTRY(__bzero_niagara4)
 	 add		%o0, 1, %o0
 .Laligned8:
 	cmp		%o1, 64 + (64 - 8)
-	ble		.Lmedium
+	ble		%XCC, .Lmedium
 	 sub		%g0, %o0, %g1
 	andcc		%g1, (64 - 1), %g1
 	brz,pn		%g1, .Laligned64
@@ -75,7 +80,7 @@ ENTRY(__bzero_niagara4)
 1:	stxa		%o4, [%o0 + %g0] ASI_BLK_INIT_QUAD_LDD_P
 	subcc		%g1, 0x40, %g1
 	stxa		%o4, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P
-	bne,pt		%icc, 1b
+	bne,pt		%XCC, 1b
 	 add		%o0, 0x40, %o0
 .Lpostloop:
 	cmp		%o1, 8
@@ -116,7 +121,7 @@ ENTRY(__bzero_niagara4)
 	stxa		%o4, [%o0 + %g2] ASI_BLK_INIT_QUAD_LDD_P
 	stxa		%o4, [%o0 + %g3] ASI_BLK_INIT_QUAD_LDD_P
 	stxa		%o4, [%o0 + %o5] ASI_BLK_INIT_QUAD_LDD_P
-	bne,pt		%icc, 1b
+	bne,pt		%XCC, 1b
 	 add		%o0, 0x30, %o0
 	ba,a,pt		%icc, .Lpostloop
 END(__bzero_niagara4)

Index Nav:	[Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav:	[Date Prev] [Date Next]	[Thread Prev] [Thread Next]