Re: [PATCH][BZ #18740] Fix for SSE vector math tests run on non SSE4.1 machines

["H.J. Lu" <hjl dot tools at gmail dot com>]

On Thu, Jul 30, 2015 at 7:27 AM, Andrew Senkevich
<andrew.n.senkevich@gmail.com> wrote:
> Hi,
>
> we can build SSE vector math tests with -msse2 because ifunc in vector
> function itself selects SSE2 or SSE4 implementation to test.
>
> 2015-07-30  Andrew Senkevich  <andrew.senkevich@intel.com>
>
>         [BZ #18740]
>         * sysdeps/x86_64/fpu/Makefile (double-vlen2-arch-ext-cflags,
>         float-vlen4-arch-ext-cflags): Use -msee2 instead of -msse4.
>
> diff --git a/ChangeLog b/ChangeLog
> index bcb14cf..b5c21b5 100644
> --- a/ChangeLog
> +++ b/ChangeLog
> @@ -1,3 +1,9 @@
> +2015-07-30  Andrew Senkevich  <andrew.senkevich@intel.com>
> +
> +       [BZ #18740]
> +       * sysdeps/x86_64/fpu/Makefile (double-vlen2-arch-ext-cflags,
> +       float-vlen4-arch-ext-cflags): Use -msee2 instead of -msse4.
> +
>  2015-07-30  Mike Frysinger  <vapier@gentoo.org>
>
>         * sysdeps/hppa/nptl/bits/pthreadtypes.h (pthread_mutex_t): Change
> diff --git a/sysdeps/x86_64/fpu/Makefile b/sysdeps/x86_64/fpu/Makefile
> index e270b8a..28802dd 100644
> --- a/sysdeps/x86_64/fpu/Makefile
> +++ b/sysdeps/x86_64/fpu/Makefile
> @@ -33,12 +33,12 @@ ifeq (yes,$(config-cflags-avx512))
>  libmvec-tests += double-vlen8 float-vlen16
>  endif
>
> -double-vlen2-arch-ext-cflags = -msse4
> +double-vlen2-arch-ext-cflags = -msse2
>  double-vlen4-arch-ext-cflags = -mavx
>  double-vlen4-arch-ext2-cflags = -mavx2
>  double-vlen8-arch-ext-cflags = -mavx512f
>
> -float-vlen4-arch-ext-cflags = -msse4
> +float-vlen4-arch-ext-cflags = -msse2
>  float-vlen8-arch-ext-cflags = -mavx
>  float-vlen8-arch-ext2-cflags = -mavx2
>  float-vlen16-arch-ext-cflags = -mavx512f
>

SSE2 is the default for x86-64.  Please just remove the line.


-- 
H.J.