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[PATCH 13/13] AArch64: Cleanup fenv implementation
- From: "Wilco Dijkstra" <wdijkstr at arm dot com>
- To: <libc-alpha at sourceware dot org>
- Date: Thu, 23 Oct 2014 18:36:30 +0100
- Subject: [PATCH 13/13] AArch64: Cleanup fenv implementation
- Authentication-results: sourceware.org; auth=none
Improve feenableexcept performance - avoid an unnecessary FPCR read in case
the FPCR does not change. Also improve the logic of the return value.
ChangeLog:
2014-10-23 Wilco Dijkstra <wdijkstr@arm.com>
* sysdeps/aarch64/fpu/feenablxcpt.c (feenableexcept):
Optimize to avoid an unnecessary FPCR read.
---
sysdeps/aarch64/fpu/feenablxcpt.c | 16 +++++++---------
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/sysdeps/aarch64/fpu/feenablxcpt.c b/sysdeps/aarch64/fpu/feenablxcpt.c
index 763248f..dfb4120 100644
--- a/sysdeps/aarch64/fpu/feenablxcpt.c
+++ b/sysdeps/aarch64/fpu/feenablxcpt.c
@@ -24,24 +24,22 @@ feenableexcept (int excepts)
{
fpu_control_t fpcr;
fpu_control_t fpcr_new;
+ fpu_control_t updated_fpcr;
_FPU_GETCW (fpcr);
excepts &= FE_ALL_EXCEPT;
fpcr_new = fpcr | (excepts << FE_EXCEPT_SHIFT);
if (fpcr != fpcr_new)
- _FPU_SETCW (fpcr_new);
-
- /* Trapping exceptions are optional in AArch64 the relevant enable
- bits in FPCR are RES0 hence the absence of support can be
- detected by reading back the FPCR and comparing with the required
- value. */
- if (excepts)
{
- fpu_control_t updated_fpcr;
+ _FPU_SETCW (fpcr_new);
+ /* Trapping exceptions are optional in AArch64; the relevant enable
+ bits in FPCR are RES0 hence the absence of support can be detected
+ by reading back the FPCR and comparing with the required value. */
_FPU_GETCW (updated_fpcr);
- if (((updated_fpcr >> FE_EXCEPT_SHIFT) & excepts) != excepts)
+
+ if (fpcr_new & ~updated_fpcr)
return -1;
}
--
1.9.1