Re: powerpc pthread_once bug fix

[Steven Munroe <munroesj at linux dot vnet dot ibm dot com>]

On Thu, 2012-08-30 at 13:06 -0600, Jeff Law wrote:
> On 07/11/2012 05:36 AM, Alan Modra wrote:
> > This fixes some bugs in the powerpc pthread_once code.  Ref
> > gcc.gnu.org/bugzilla/show_bug.cgi?id=52839#c10
> >
> > Release barriers are needed to ensure any memory written by
> > init_routine is seen by other threads before *once_control changes.
> > In the case of clear_once_control we need to flush any partially
> > written state.
> >
> > 2012-06-28  Alan Modra  <amodra@gmail.com>
> >
> > 	* sysdeps/unix/sysv/linux/powerpc/pthread_once.c (__pthread_once):
> > 	Add release barrier before setting once_control to say
> > 	initialisation is done.  Add hints on lwarx.  Use macro in
> > 	place of isync.
> > 	(clear_once_control): Add release barrier.
> FWIW, I saw hangs with this too, both ppc and ppc64.  It's got something 
> to do with that last hunk which replaced the atomic_increment call with 
> an asm which appears to impmlement an atomic_read_barrier + 
> atomic_increment.
> 
> My PPC-fu is largely gone.  The only oddities I see are the lack of a 
> memory clobber and using GENERAL_REGS instead of BASE_REGS for 
> once_control.  Is there something special about r0 in lwarx/stwcx insns 
> on PPC?

Since Alan is a sleep I will try to the answer. =M should imply the
memory clobber but it would not hurt to be explicit. lwarx/stwcx. are
index forms and r0 as the 2nd parm implies no index, just a base address
in the 3rd register parm. The 4th lwarx parm (MUTEX_HINT_ACQ) is a cache
line optimization.

But the important part is replacing the atomic_increment macro, which
does not include any memory barrier, with a explicit atomic add with a
leading release (___lll_rel_instr) barrier.

With this patch pthread_once implements the required acquire / release
semantics.
>