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[PATCH] Mark sparc %fsr load and store inline asms as volatile.
- From: David Miller <davem at davemloft dot net>
- To: libc-alpha at sourceware dot org
- Date: Fri, 11 May 2012 17:06:55 -0400 (EDT)
- Subject: [PATCH] Mark sparc %fsr load and store inline asms as volatile.
A non-multiarch sparc build gets test-float failures for fmaf, mostly
to do with lack of proper exception reporting.
The dbl-64/s_fmaf.c code has a flow like this:
double multiply
save FSR state, change rounding
double addition
capture and report exceptions, restore FSR state
But because the __fenv_stfsr() was not marked volatile, GCC moved
the %fsr read to be before the double multiply. And this is what
causes all of the aforementioned test-float failures.
There is no reasonable way to inform the compiler that an inline
asm depends purely upon all FPU operations, I've marked all %fsr
loads and stores as volatile.
Committed to master.
* sysdeps/sparc/fpu/bits/fenv.h (__fenv_stfsr): Add __volatile__.
* sysdeps/sparc/fpu/fpu_control.h (_FPU_GETCW): Likewise.
(_FPU_SETCW): Likewise.
---
ChangeLog | 6 ++++++
sysdeps/sparc/fpu/bits/fenv.h | 4 ++--
sysdeps/sparc/fpu/fpu_control.h | 8 ++++----
3 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/ChangeLog b/ChangeLog
index dcc28d5..d3a2a8e 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,9 @@
+2012-05-11 David S. Miller <davem@davemloft.net>
+
+ * sysdeps/sparc/fpu/bits/fenv.h (__fenv_stfsr): Add __volatile__.
+ * sysdeps/sparc/fpu/fpu_control.h (_FPU_GETCW): Likewise.
+ (_FPU_SETCW): Likewise.
+
2012-05-10 H.J. Lu <hongjiu.lu@intel.com>
* sysdeps/x86_64/dl-trampoline.S: Check if RTLD_SAVESPACE_SSE
diff --git a/sysdeps/sparc/fpu/bits/fenv.h b/sysdeps/sparc/fpu/bits/fenv.h
index 2168de5..0e2a9b9 100644
--- a/sysdeps/sparc/fpu/bits/fenv.h
+++ b/sysdeps/sparc/fpu/bits/fenv.h
@@ -76,9 +76,9 @@ typedef unsigned long int fenv_t;
/* For internal use only: access the fp state register. */
#if __WORDSIZE == 64
-# define __fenv_stfsr(X) __asm__ ("stx %%fsr,%0" : "=m" (X))
+# define __fenv_stfsr(X) __asm__ __volatile__ ("stx %%fsr,%0" : "=m" (X))
# define __fenv_ldfsr(X) __asm__ __volatile__ ("ldx %0,%%fsr" : : "m" (X))
#else
-# define __fenv_stfsr(X) __asm__ ("st %%fsr,%0" : "=m" (X))
+# define __fenv_stfsr(X) __asm__ __volatile__ ("st %%fsr,%0" : "=m" (X))
# define __fenv_ldfsr(X) __asm__ __volatile__ ("ld %0,%%fsr" : : "m" (X))
#endif
diff --git a/sysdeps/sparc/fpu/fpu_control.h b/sysdeps/sparc/fpu/fpu_control.h
index c8bb503..26c08e9 100644
--- a/sysdeps/sparc/fpu/fpu_control.h
+++ b/sysdeps/sparc/fpu/fpu_control.h
@@ -59,11 +59,11 @@
typedef unsigned long int fpu_control_t;
#if __WORDSIZE == 64
-# define _FPU_GETCW(cw) __asm__ ("stx %%fsr,%0" : "=m" (*&cw))
-# define _FPU_SETCW(cw) __asm__ ("ldx %0,%%fsr" : : "m" (*&cw))
+# define _FPU_GETCW(cw) __asm__ __volatile__ ("stx %%fsr,%0" : "=m" (*&cw))
+# define _FPU_SETCW(cw) __asm__ __volatile__ ("ldx %0,%%fsr" : : "m" (*&cw))
#else
-# define _FPU_GETCW(cw) __asm__ ("st %%fsr,%0" : "=m" (*&cw))
-# define _FPU_SETCW(cw) __asm__ ("ld %0,%%fsr" : : "m" (*&cw))
+# define _FPU_GETCW(cw) __asm__ __volatile__ ("st %%fsr,%0" : "=m" (*&cw))
+# define _FPU_SETCW(cw) __asm__ __volatile__ ("ld %0,%%fsr" : : "m" (*&cw))
#endif
/* Default control word set at startup. */
--
1.7.10