Re: Let's see if _this_ works...

[Marcus Sundberg <erammsu at kieraypc01 dot p dot y dot ki dot era dot ericsson dot se>]

Andreas Jaeger <aj@suse.de> writes:

> >>>>> Geoff Keating writes:
> 
>  > This is the new improved version of the ppc PLT improvement.  It's
>  > much nicer, with one exception.  Please test it a lot, I would like it
>  > to be in the next minor release.
> 
> Has this now been resolved?  I know there where some comments from
> Marcus Sundberg but AFAIK the patch is still not integrated.  I really
> would like to see the open bug report closed which triggered this.

This patch (against 2.1.2+Geoff's patch) is needed to support embedded
PPC processors:

diff -ur orig/glibc-2.1.2/sysdeps/powerpc/dl-machine.c glibc-2.1.2/sysdeps/powerpc/dl-machine.c
--- orig/glibc-2.1.2/sysdeps/powerpc/dl-machine.c	Thu Dec 30 14:31:52 1999
+++ glibc-2.1.2/sysdeps/powerpc/dl-machine.c	Thu Dec 30 14:34:24 1999
@@ -298,12 +298,12 @@
 	 Most of the PLT shouldn't be in the instruction cache, but
 	 there may be a little overlap at the start and the end.
 
-	 Assumes the cache line size is at least 32 bytes, or at least
-	 that dcbst and icbi apply to 32-byte lines.  At present, all
-	 PowerPC processors have line sizes of exactly 32 bytes.  */
+	 Assumes the cache line size is at least 16 bytes, or at least
+	 that dcbst and icbi apply to 16-byte lines.  At present, all
+	 PowerPC processors have line sizes of either 16 or 32 bytes.  */
 
       size_modified = lazy ? rel_offset_words : 6;
-      for (i = 0; i < size_modified; i += 8)
+      for (i = 0; i < size_modified; i += 4)
 	PPC_DCBST (plt + i);
       PPC_DCBST (plt + size_modified - 1);
       PPC_SYNC;


In addition to that I never received any comments on the mail below:

Geoff Keating <geoffk@ozemail.com.au> writes:
> > Then there is the issue of memset.S, which also assumes a cache line
> > size of 32 bytes. Currently I simply move it away when I build glibc,
> > but it would be nice if that could be solved as well. Now that there
> > is FP-emulation for PPC in the kernel the cache line issue is the
> > only thing preventing the same glibc binary from running on 8xx and
> > other PPC cpus.
> 
> I really don't want to halve the speed of bzero() for all machines.
> Any other ideas?

Make a check on the first call to memset and cache the result in a
static variable like getpwd() does?

The problem is that Motorola seems to think that knowing what CPU
you're running on compromises system-security, so they made the PVR
only readble from supervisor mode...

The best I can think of is to export the PVR from kernel with the
sysctl interface (only a single syscall to read it as opposed to
a /proc file or similiar).

//Marcus
-- 
Signature under construction, please come back later.