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GNU C Library master sources branch hjl/tunables/master created. glibc-2.25-397-g9506057
- From: hjl at sourceware dot org
- To: glibc-cvs at sourceware dot org
- Date: 4 Jun 2017 15:57:38 -0000
- Subject: GNU C Library master sources branch hjl/tunables/master created. glibc-2.25-397-g9506057
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http://sourceware.org/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=9506057c4b6825bb934dfef42ffd29e0cc1da478
commit 9506057c4b6825bb934dfef42ffd29e0cc1da478
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Tue May 23 20:22:13 2017 -0700
Add TUNABLES to control IFUNC selection and cache sizes
The current IFUNC selection is based on microbenchmarks in glibc. It
should give the best performance for most workloads. But other choices
may have better performance for a particular workload or on the hardware
which wasn't available at the selection was made. The environment
variable, GLIBC_IFUNC=-xxx,yyy,-zzz...., can be used to enable CPU/ARCH
feature yyy, disable CPU/ARCH feature yyy and zzz, where the feature
name is case-sensitive and has to match the ones in cpu-features.h. It
can be used by glibc developers to override the IFUNC selection to tune
for a new processor or improve performance for a particular workload.
It isn't intended for normal end users.
NOTE: the IFUNC selection may change over time. Please check all
multiarch implementations when experimenting.
2017-05-27 H.J. Lu <hongjiu.lu@intel.com>
Erich Elsen <eriche@google.com>
* elf/dl-tunables.list: Add a "tune" namespace.
* sysdeps/unix/sysv/linux/x86/dl-sysdep.c: New file.
* sysdeps/x86/cpu-tunables.c: Likewise.
* sysdeps/x86/cacheinfo.c (TUNABLE_NAMESPACE): New.
Include <elf/dl-tunables.h> for TUNABLES is on.
Include <string.h> and <stdlib.h> if TUNABLES is off.
(__environ): New.
(init_cacheinfo): Use TUNABLES to set data cache size, shared
cache size and non temporal threshold if TUNABLES is on. Search
the environment strings to set data cache size, shared cache
size and non temporal threshold if TUNABLES is off.
* sysdeps/x86/cpu-features.c (TUNABLE_NAMESPACE): New.
(DL_TUNABLE_CALLBACK (set_ifunc)): Likewise.
Include <elf/dl-tunables.h> for TUNABLES is on.
Include <string.h> and <unistd.h> if TUNABLES is off.
(__environ): New.
(_dl_x86_set_ifunc): Likewise.
(init_cpu_features): Use TUNABLE_SET_VAL_WITH_CALLBACK if
TUNABLES is on. Call _dl_x86_set_ifunc for GLIBC_IFUNC= if
TUNABLES is off.
* sysdeps/x86/cpu-features.h (DEFAULT_MEMCMP): New.
diff --git a/elf/dl-tunables.list b/elf/dl-tunables.list
index b9f1488..0401087 100644
--- a/elf/dl-tunables.list
+++ b/elf/dl-tunables.list
@@ -77,4 +77,26 @@ glibc {
security_level: SXID_IGNORE
}
}
+ tune {
+ ifunc {
+ type: STRING
+ env_alias: GLIBC_IFUNC
+ security_level: SXID_IGNORE
+ }
+ non_temporal_threshold {
+ type: SIZE_T
+ env_alias: GLIBC_NON_TEMPORAL_THRESHOLD
+ security_level: SXID_IGNORE
+ }
+ data_cache_size {
+ type: SIZE_T
+ env_alias: GLIBC_DATA_CACHE_SIZE
+ security_level: SXID_IGNORE
+ }
+ shared_cache_size {
+ type: SIZE_T
+ env_alias: GLIBC_SHARED_CACHE_SIZE
+ security_level: SXID_IGNORE
+ }
+ }
}
diff --git a/sysdeps/unix/sysv/linux/x86/dl-sysdep.c b/sysdeps/unix/sysv/linux/x86/dl-sysdep.c
new file mode 100644
index 0000000..64eb0d7
--- /dev/null
+++ b/sysdeps/unix/sysv/linux/x86/dl-sysdep.c
@@ -0,0 +1,21 @@
+/* Operating system support for run-time dynamic linker. X86 version.
+ Copyright (C) 2017 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+#include <config.h>
+#include <sysdeps/x86/cpu-tunables.c>
+#include <sysdeps/unix/sysv/linux/dl-sysdep.c>
diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c
index 8000fd1..5d1ecbc 100644
--- a/sysdeps/x86/cacheinfo.c
+++ b/sysdeps/x86/cacheinfo.c
@@ -25,6 +25,15 @@
#include <cpuid.h>
#include <init-arch.h>
+#if HAVE_TUNABLES
+# define TUNABLE_NAMESPACE tune
+# include <elf/dl-tunables.h>
+#else
+# include <string.h>
+# include <stdlib.h>
+extern char **__environ;
+#endif
+
static const struct intel_02_cache_info
{
unsigned char idx;
@@ -752,6 +761,43 @@ intel_bug_no_cache_info:
#endif
}
+ /* Data cache size for use in memory and string routines, typically
+ L1 size. */
+ long int data_cache_size = 0;
+ /* Shared cache size for use in memory and string routines, typically
+ L2 or L3 size. */
+ long int shared_cache_size = 0;
+ /* Threshold to use non temporal store. */
+ long int non_temporal_threshold = 0;
+
+#if HAVE_TUNABLES
+ TUNABLE_SET_VAL (non_temporal_threshold, &non_temporal_threshold);
+ TUNABLE_SET_VAL (data_cache_size, &data_cache_size);
+ TUNABLE_SET_VAL (shared_cache_size, &shared_cache_size);
+#else
+ if (__glibc_likely (__environ != NULL)
+ && !__builtin_expect (__libc_enable_secure, 0))
+ {
+ char **runp = __environ;
+ char *envline;
+
+ while (*runp != NULL)
+ {
+ envline = *runp;
+ if (!memcmp (envline, "GLIBC_NON_TEMPORAL_THRESHOLD=", 29))
+ non_temporal_threshold = strtol (&envline[29], NULL, 0);
+ else if (!memcmp (envline, "GLIBC_DATA_CACHE_SIZE=", 22))
+ data_cache_size = strtol (&envline[22], NULL, 0);
+ else if (!memcmp (envline, "GLIBC_SHARED_CACHE_SIZE=", 24))
+ shared_cache_size = strtol (&envline[24], NULL, 0);
+ runp++;
+ }
+ }
+#endif
+
+ if (data_cache_size != 0)
+ data = data_cache_size;
+
if (data > 0)
{
__x86_raw_data_cache_size_half = data / 2;
@@ -762,6 +808,9 @@ intel_bug_no_cache_info:
__x86_data_cache_size = data;
}
+ if (shared_cache_size != 0)
+ shared = shared_cache_size;
+
if (shared > 0)
{
__x86_raw_shared_cache_size_half = shared / 2;
@@ -777,7 +826,9 @@ intel_bug_no_cache_info:
store becomes faster on a 8-core processor. This is the 3/4 of the
total shared cache size. */
__x86_shared_non_temporal_threshold
- = __x86_shared_cache_size * threads * 3 / 4;
+ = (non_temporal_threshold != 0
+ ? non_temporal_threshold
+ : __x86_shared_cache_size * threads * 3 / 4);
}
#endif
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index b481f50..97695a2 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -20,6 +20,19 @@
#include <cpu-features.h>
#include <dl-hwcap.h>
+#if HAVE_TUNABLES
+# define TUNABLE_NAMESPACE tune
+# include <elf/dl-tunables.h>
+
+extern void DL_TUNABLE_CALLBACK (set_ifunc) (tunable_val_t *)
+ attribute_hidden;
+#else
+# include <string.h>
+# include <unistd.h>
+extern char **__environ attribute_hidden;
+extern void _dl_x86_set_ifunc (const char *) attribute_hidden;
+#endif
+
static void
get_common_indeces (struct cpu_features *cpu_features,
unsigned int *family, unsigned int *model,
@@ -312,6 +325,29 @@ no_cpuid:
cpu_features->model = model;
cpu_features->kind = kind;
+#if HAVE_TUNABLES
+ TUNABLE_SET_VAL_WITH_CALLBACK (ifunc, NULL, set_ifunc);
+#else
+ if (__glibc_likely (__environ != NULL)
+ && !__builtin_expect (__libc_enable_secure, 0))
+ {
+ char **runp = __environ;
+ char *envline;
+
+ while (*runp != NULL)
+ {
+ envline = *runp;
+ if (!DEFAULT_MEMCMP (envline, "GLIBC_IFUNC=",
+ sizeof ("GLIBC_IFUNC=") - 1))
+ {
+ _dl_x86_set_ifunc (envline + sizeof ("GLIBC_IFUNC=") - 1);
+ break;
+ }
+ runp++;
+ }
+ }
+#endif
+
#if IS_IN (rtld)
/* Reuse dl_platform, dl_hwcap and dl_hwcap_mask for x86. */
GLRO(dl_platform) = NULL;
diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h
index 31c7c80..851d137 100644
--- a/sysdeps/x86/cpu-features.h
+++ b/sysdeps/x86/cpu-features.h
@@ -227,6 +227,18 @@ extern const struct cpu_features *__get_cpu_features (void)
# define __get_cpu_features() (&GLRO(dl_x86_cpu_features))
# endif
+/* We can't use IFUNC memcmp in init_cpu_features from libc.a since
+ IFUNC must be set up by init_cpu_features. */
+# if defined USE_MULTIARCH && !defined SHARED
+# ifdef __x86_64__
+# define DEFAULT_MEMCMP __memcmp_sse2
+# else
+# define DEFAULT_MEMCMP __memcmp_ia32
+# endif
+extern __typeof (memcmp) DEFAULT_MEMCMP;
+# else
+# define DEFAULT_MEMCMP memcmp
+# endif
/* Only used directly in cpu-features.c. */
# define CPU_FEATURES_CPU_P(ptr, name) \
diff --git a/sysdeps/x86/cpu-tunables.c b/sysdeps/x86/cpu-tunables.c
new file mode 100644
index 0000000..b98f8e7
--- /dev/null
+++ b/sysdeps/x86/cpu-tunables.c
@@ -0,0 +1,322 @@
+/* CPU feature tuning.
+ This file is part of the GNU C Library.
+ Copyright (C) 2017 Free Software Foundation, Inc.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+#include <string.h>
+#if HAVE_TUNABLES
+# define TUNABLE_NAMESPACE tune
+# include <elf/dl-tunables.h>
+#endif
+#include <cpu-features.h>
+#include <ldsodefs.h>
+
+#define CHECK_GLIBC_IFUNC_CPU_OFF(f, cpu_features, name, len) \
+ _Static_assert (sizeof (#name) - 1 == len, #name " != " #len); \
+ if (!DEFAULT_MEMCMP (f, #name, len)) \
+ { \
+ cpu_features->cpuid[index_cpu_##name].reg_##name \
+ &= ~bit_cpu_##name; \
+ break; \
+ }
+
+/* Disable an ARCH feature NAME. We don't enable an ARCH feature which
+ isn't available. */
+#define CHECK_GLIBC_IFUNC_ARCH_OFF(f, cpu_features, name, len) \
+ _Static_assert (sizeof (#name) - 1 == len, #name " != " #len); \
+ if (!DEFAULT_MEMCMP (f, #name, len)) \
+ { \
+ cpu_features->feature[index_arch_##name] \
+ &= ~bit_arch_##name; \
+ break; \
+ }
+
+/* Enable/disable an ARCH feature NAME. */
+#define CHECK_GLIBC_IFUNC_ARCH_BOTH(f, cpu_features, name, disable, \
+ len) \
+ _Static_assert (sizeof (#name) - 1 == len, #name " != " #len); \
+ if (!DEFAULT_MEMCMP (f, #name, len)) \
+ { \
+ if (disable) \
+ cpu_features->feature[index_arch_##name] \
+ &= ~bit_arch_##name; \
+ else \
+ cpu_features->feature[index_arch_##name] \
+ |= bit_arch_##name; \
+ break; \
+ }
+
+/* Enable/disable an ARCH feature NAME. Enable an ARCH feature only
+ if the ARCH feature NEED is also enabled. */
+#define CHECK_GLIBC_IFUNC_ARCH_NEED_ARCH_BOTH(f, cpu_features, name, \
+ need, disable, len) \
+ _Static_assert (sizeof (#name) - 1 == len, #name " != " #len); \
+ if (!DEFAULT_MEMCMP (f, #name, len)) \
+ { \
+ if (disable) \
+ cpu_features->feature[index_arch_##name] \
+ &= ~bit_arch_##name; \
+ else if (CPU_FEATURES_ARCH_P (cpu_features, need)) \
+ cpu_features->feature[index_arch_##name] \
+ |= bit_arch_##name; \
+ break; \
+ }
+
+/* Enable/disable an ARCH feature NAME. Enable an ARCH feature only
+ if the CPU feature NEED is also enabled. */
+#define CHECK_GLIBC_IFUNC_ARCH_NEED_CPU_BOTH(f, cpu_features, name, \
+ need, disable, len) \
+ _Static_assert (sizeof (#name) - 1 == len, #name " != " #len); \
+ if (!DEFAULT_MEMCMP (f, #name, len)) \
+ { \
+ if (disable) \
+ cpu_features->feature[index_arch_##name] \
+ &= ~bit_arch_##name; \
+ else if (CPU_FEATURES_CPU_P (cpu_features, need)) \
+ cpu_features->feature[index_arch_##name] \
+ |= bit_arch_##name; \
+ break; \
+ }
+
+#if HAVE_TUNABLES
+static
+#else
+attribute_hidden
+#endif
+void
+_dl_x86_set_ifunc (const char *p)
+{
+ /* The current IFUNC selection is based on microbenchmarks in glibc.
+ It should give the best performance for most workloads. But other
+ choices may have better performance for a particular workload or on
+ the hardware which wasn't available when the selection was made.
+ The environment variable, GLIBC_IFUNC=-xxx,yyy,-zzz...., can be
+ used to enable CPU/ARCH feature yyy, disable CPU/ARCH feature yyy
+ and zzz, where the feature name is case-sensitive and has to match
+ the ones in cpu-features.h. It can be used by glibc developers to
+ tune for a new processor or override the IFUNC selection to improve
+ performance for a particular workload.
+
+ Since all CPU/ARCH features are hardware optimizations without
+ security implication, except for Prefer_MAP_32BIT_EXEC, which can
+ only be disabled, we check GLIBC_IFUNC for programs, including
+ set*id ones.
+
+ NOTE: the IFUNC selection may change over time. Please check all
+ multiarch implementations when experimenting. */
+
+ struct cpu_features *cpu_features = &GLRO(dl_x86_cpu_features);
+ const char *end = p + strlen (p);
+ size_t len;
+
+ do
+ {
+ const char *c, *n;
+ bool disable;
+ size_t nl;
+
+ for (c = p; *c != ','; c++)
+ if (c >= end)
+ break;
+
+ len = c - p;
+ disable = *p == '-';
+ if (disable)
+ {
+ n = p + 1;
+ nl = len - 1;
+ }
+ else
+ {
+ n = p;
+ nl = len;
+ }
+ switch (nl)
+ {
+ default:
+ break;
+ case 3:
+ if (disable)
+ {
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, AVX, 3);
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, CX8, 3);
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, FMA, 3);
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, HTT, 3);
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, RTM, 3);
+ }
+ break;
+ case 4:
+ if (disable)
+ {
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, AVX2, 4);
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, BMI1, 4);
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, BMI2, 4);
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, CMOV, 4);
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, ERMS, 4);
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, FMA4, 4);
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, SSE2, 4);
+ CHECK_GLIBC_IFUNC_ARCH_OFF (n, cpu_features, I586, 4);
+ CHECK_GLIBC_IFUNC_ARCH_OFF (n, cpu_features, I686, 4);
+ }
+ break;
+ case 5:
+ if (disable)
+ {
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, LZCNT, 5);
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, MOVBE, 5);
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, SSSE3, 5);
+ }
+ break;
+ case 6:
+ if (disable)
+ {
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, POPCNT, 6);
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, SSE4_1, 6);
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, SSE4_2, 6);
+ }
+ break;
+ case 7:
+ if (disable)
+ {
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, AVX512F, 7);
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, OSXSAVE, 7);
+ }
+ break;
+ case 8:
+ if (disable)
+ {
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, AVX512CD, 8);
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, AVX512BW, 8);
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, AVX512DQ, 8);
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, AVX512ER, 8);
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, AVX512PF, 8);
+ CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, AVX512VL, 8);
+ }
+ CHECK_GLIBC_IFUNC_ARCH_BOTH (n, cpu_features, Slow_BSF,
+ disable, 8);
+ break;
+ case 10:
+ if (disable)
+ {
+ CHECK_GLIBC_IFUNC_ARCH_OFF (n, cpu_features, AVX_Usable,
+ 10);
+ CHECK_GLIBC_IFUNC_ARCH_OFF (n, cpu_features, FMA_Usable,
+ 10);
+ }
+ break;
+ case 11:
+ if (disable)
+ {
+ CHECK_GLIBC_IFUNC_ARCH_OFF (n, cpu_features, AVX2_Usable,
+ 11);
+ CHECK_GLIBC_IFUNC_ARCH_OFF (n, cpu_features, FMA4_Usable,
+ 11);
+ }
+ CHECK_GLIBC_IFUNC_ARCH_BOTH (n, cpu_features, Prefer_ERMS,
+ disable, 11);
+ CHECK_GLIBC_IFUNC_ARCH_NEED_CPU_BOTH (n, cpu_features,
+ Slow_SSE4_2, SSE4_2,
+ disable, 11);
+ break;
+ case 14:
+ if (disable)
+ {
+ CHECK_GLIBC_IFUNC_ARCH_OFF (n, cpu_features,
+ AVX512F_Usable, 14);
+ }
+ break;
+ case 15:
+ if (disable)
+ {
+ CHECK_GLIBC_IFUNC_ARCH_OFF (n, cpu_features,
+ AVX512DQ_Usable, 15);
+ }
+ CHECK_GLIBC_IFUNC_ARCH_BOTH (n, cpu_features, Fast_Rep_String,
+ disable, 15);
+ break;
+ case 16:
+ {
+ CHECK_GLIBC_IFUNC_ARCH_NEED_ARCH_BOTH
+ (n, cpu_features, Prefer_No_AVX512, AVX512F_Usable,
+ disable, 16);
+ }
+ break;
+ case 18:
+ {
+ CHECK_GLIBC_IFUNC_ARCH_BOTH (n, cpu_features,
+ Fast_Copy_Backward, disable,
+ 18);
+ }
+ break;
+ case 19:
+ {
+ CHECK_GLIBC_IFUNC_ARCH_BOTH (n, cpu_features,
+ Fast_Unaligned_Load, disable,
+ 19);
+ CHECK_GLIBC_IFUNC_ARCH_BOTH (n, cpu_features,
+ Fast_Unaligned_Copy, disable,
+ 19);
+ }
+ break;
+ case 20:
+ {
+ CHECK_GLIBC_IFUNC_ARCH_NEED_ARCH_BOTH
+ (n, cpu_features, Prefer_No_VZEROUPPER, AVX_Usable,
+ disable, 20);
+ }
+ break;
+ case 21:
+ {
+ CHECK_GLIBC_IFUNC_ARCH_BOTH (n, cpu_features,
+ Prefer_MAP_32BIT_EXEC, disable,
+ 21);
+ }
+ break;
+ case 23:
+ {
+ CHECK_GLIBC_IFUNC_ARCH_NEED_ARCH_BOTH
+ (n, cpu_features, AVX_Fast_Unaligned_Load, AVX_Usable,
+ disable, 23);
+ }
+ break;
+ case 26:
+ {
+ CHECK_GLIBC_IFUNC_ARCH_NEED_CPU_BOTH
+ (n, cpu_features, Prefer_PMINUB_for_stringop, SSE2,
+ disable, 26);
+ }
+ break;
+ case 27:
+ {
+ CHECK_GLIBC_IFUNC_ARCH_BOTH (n, cpu_features,
+ Use_dl_runtime_resolve_slow,
+ disable, 27);
+ }
+ break;
+ }
+ p += len + 1;
+ }
+ while (p < end);
+}
+
+#if HAVE_TUNABLES
+attribute_hidden
+void
+DL_TUNABLE_CALLBACK (set_ifunc) (tunable_val_t *valp)
+{
+ _dl_x86_set_ifunc (valp->strval);
+}
+#endif
http://sourceware.org/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=672d7f057662d27b44a8ddd720c02c79d74893ec
commit 672d7f057662d27b44a8ddd720c02c79d74893ec
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Wed May 24 13:05:25 2017 -0700
x86: Don't use dl_x86_cpu_features in cacheinfo.c
Since cpu_features is available, use it instead of dl_x86_cpu_features.
* sysdeps/x86/cacheinfo.c (intel_check_word): Accept cpu_features
and use it instead of dl_x86_cpu_features.
(handle_intel): Replace maxidx with cpu_features. Pass
cpu_features to intel_check_word.
(__cache_sysconf): Pass cpu_features to handle_intel.
(init_cacheinfo): Likewise. Use cpu_features instead of
dl_x86_cpu_features.
diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c
index f66f2b8..8000fd1 100644
--- a/sysdeps/x86/cacheinfo.c
+++ b/sysdeps/x86/cacheinfo.c
@@ -126,7 +126,8 @@ intel_02_known_compare (const void *p1, const void *p2)
static long int
__attribute__ ((noinline))
intel_check_word (int name, unsigned int value, bool *has_level_2,
- bool *no_level_2_or_3)
+ bool *no_level_2_or_3,
+ const struct cpu_features *cpu_features)
{
if ((value & 0x80000000) != 0)
/* The register value is reserved. */
@@ -204,8 +205,8 @@ intel_check_word (int name, unsigned int value, bool *has_level_2,
/* Intel reused this value. For family 15, model 6 it
specifies the 3rd level cache. Otherwise the 2nd
level cache. */
- unsigned int family = GLRO(dl_x86_cpu_features).family;
- unsigned int model = GLRO(dl_x86_cpu_features).model;
+ unsigned int family = cpu_features->family;
+ unsigned int model = cpu_features->model;
if (family == 15 && model == 6)
{
@@ -255,8 +256,10 @@ intel_check_word (int name, unsigned int value, bool *has_level_2,
static long int __attribute__ ((noinline))
-handle_intel (int name, unsigned int maxidx)
+handle_intel (int name, const struct cpu_features *cpu_features)
{
+ unsigned int maxidx = cpu_features->max_cpuid;
+
/* Return -1 for older CPUs. */
if (maxidx < 2)
return -1;
@@ -287,19 +290,23 @@ handle_intel (int name, unsigned int maxidx)
}
/* Process the individual registers' value. */
- result = intel_check_word (name, eax, &has_level_2, &no_level_2_or_3);
+ result = intel_check_word (name, eax, &has_level_2,
+ &no_level_2_or_3, cpu_features);
if (result != 0)
return result;
- result = intel_check_word (name, ebx, &has_level_2, &no_level_2_or_3);
+ result = intel_check_word (name, ebx, &has_level_2,
+ &no_level_2_or_3, cpu_features);
if (result != 0)
return result;
- result = intel_check_word (name, ecx, &has_level_2, &no_level_2_or_3);
+ result = intel_check_word (name, ecx, &has_level_2,
+ &no_level_2_or_3, cpu_features);
if (result != 0)
return result;
- result = intel_check_word (name, edx, &has_level_2, &no_level_2_or_3);
+ result = intel_check_word (name, edx, &has_level_2,
+ &no_level_2_or_3, cpu_features);
if (result != 0)
return result;
}
@@ -437,7 +444,7 @@ __cache_sysconf (int name)
const struct cpu_features *cpu_features = __get_cpu_features ();
if (cpu_features->kind == arch_kind_intel)
- return handle_intel (name, cpu_features->max_cpuid);
+ return handle_intel (name, cpu_features);
if (cpu_features->kind == arch_kind_amd)
return handle_amd (name);
@@ -494,14 +501,14 @@ init_cacheinfo (void)
if (cpu_features->kind == arch_kind_intel)
{
- data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, max_cpuid);
+ data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, cpu_features);
- long int core = handle_intel (_SC_LEVEL2_CACHE_SIZE, max_cpuid);
+ long int core = handle_intel (_SC_LEVEL2_CACHE_SIZE, cpu_features);
bool inclusive_cache = true;
/* Try L3 first. */
level = 3;
- shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, max_cpuid);
+ shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, cpu_features);
/* Number of logical processors sharing L2 cache. */
int threads_l2;
@@ -531,8 +538,8 @@ init_cacheinfo (void)
highest cache level. */
if (max_cpuid >= 4)
{
- unsigned int family = GLRO(dl_x86_cpu_features).family;
- unsigned int model = GLRO(dl_x86_cpu_features).model;
+ unsigned int family = cpu_features->family;
+ unsigned int model = cpu_features->model;
int i = 0;
@@ -675,7 +682,7 @@ intel_bug_no_cache_info:
level. */
threads
- = ((GLRO(dl_x86_cpu_features).cpuid[COMMON_CPUID_INDEX_1].ebx
+ = ((cpu_features->cpuid[COMMON_CPUID_INDEX_1].ebx
>> 16) & 0xff);
}
-----------------------------------------------------------------------
hooks/post-receive
--
GNU C Library master sources