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GNU C Library master sources branch hjl/tunables/master created. glibc-2.25-372-gcfea338


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The branch, hjl/tunables/master has been created
        at  cfea3382668398e94faa9bce77f44571b2346273 (commit)

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http://sourceware.org/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=cfea3382668398e94faa9bce77f44571b2346273

commit cfea3382668398e94faa9bce77f44571b2346273
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Mon Jun 27 15:13:50 2016 -0700

    Add TUNABLES to control IFUNC selection
    
    The current IFUNC selection is based on microbenchmarks in glibc.  It
    should give the best performance for most workloads.  But other choices
    may have better performance for a particular workload or on the hardware
    which wasn't available at the selection was made.  The environment
    variable, GLIBC_IFUNC=-xxx,yyy,-zzz...., can be used to enable CPU/ARCH
    feature yyy, disable CPU/ARCH feature yyy and zzz, where the feature
    name is case-sensitive and has to match the ones in cpu-features.h.  It
    can be used by glibc developers to override the IFUNC selection to tune
    for a new processor or improve performance for a particular workload.
    It isn't intended for normal end users.
    
    NOTE: the IFUNC selection may change over time.  Please check all
    multiarch implementations when experimenting.
    
    	* sysdeps/unix/sysv/linux/x86/dl-sysdep.c: New file.
    	* sysdeps/x86/cpu-tunables.c: Likewise.
    	* sysdeps/x86/dl-tunables.list: Likewise.
    	* sysdeps/x86/cpu-features.c (TUNABLE_NAMESPACE): New.
    	(DL_TUNABLE_CALLBACK (set_ifunc)): Likewise.
    	Include <elf/dl-tunables.h> for TUNABLES is on.
    	Include <string.h> and <unistd.h> if TUNABLES is off.
    	(__environ): New.
    	(set_ifunc): Likewise.
    	(init_cpu_features): Use TUNABLE_SET_VAL_WITH_CALLBACK if
    	TUNABLES is on.  Call set_ifunc for GLIBC_IFUNC= if
    	TUNABLES is off.

diff --git a/sysdeps/unix/sysv/linux/x86/dl-sysdep.c b/sysdeps/unix/sysv/linux/x86/dl-sysdep.c
new file mode 100644
index 0000000..64eb0d7
--- /dev/null
+++ b/sysdeps/unix/sysv/linux/x86/dl-sysdep.c
@@ -0,0 +1,21 @@
+/* Operating system support for run-time dynamic linker.  X86 version.
+   Copyright (C) 2017 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include <config.h>
+#include <sysdeps/x86/cpu-tunables.c>
+#include <sysdeps/unix/sysv/linux/dl-sysdep.c>
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index b481f50..dfa6801 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -20,6 +20,23 @@
 #include <cpu-features.h>
 #include <dl-hwcap.h>
 
+/* Since __environ is set after init_cpu_features is called in libc.a,
+   CPU feature tuning is only supported in libc.so.  */
+#ifdef SHARED
+#if HAVE_TUNABLES
+# define TUNABLE_NAMESPACE x86
+# include <elf/dl-tunables.h>
+
+extern void DL_TUNABLE_CALLBACK (set_ifunc) (tunable_val_t *)
+  attribute_hidden;
+# else
+# include <string.h>
+# include <unistd.h>
+extern char **__environ attribute_hidden;
+extern void set_ifunc (const char *) attribute_hidden;
+# endif
+#endif
+
 static void
 get_common_indeces (struct cpu_features *cpu_features,
 		    unsigned int *family, unsigned int *model,
@@ -312,6 +329,31 @@ no_cpuid:
   cpu_features->model = model;
   cpu_features->kind = kind;
 
+#ifdef  SHARED
+# if HAVE_TUNABLES
+  TUNABLE_SET_VAL_WITH_CALLBACK (ifunc, NULL, set_ifunc);
+# else
+  if (__glibc_likely (__environ != NULL)
+      && !__builtin_expect (__libc_enable_secure, 0))
+    {
+      char **runp = __environ;
+      char *envline;
+
+      while (*runp != NULL)
+	{
+	  envline = *runp;
+	  if (!memcmp (envline, "GLIBC_IFUNC=",
+		       sizeof ("GLIBC_IFUNC=") - 1))
+	  {
+	    set_ifunc (envline + sizeof ("GLIBC_IFUNC=") - 1);
+	    break;
+	  }
+	  runp++;
+	}
+    }
+# endif
+#endif
+
 #if IS_IN (rtld)
   /* Reuse dl_platform, dl_hwcap and dl_hwcap_mask for x86.  */
   GLRO(dl_platform) = NULL;
diff --git a/sysdeps/x86/cpu-tunables.c b/sysdeps/x86/cpu-tunables.c
new file mode 100644
index 0000000..d29e817
--- /dev/null
+++ b/sysdeps/x86/cpu-tunables.c
@@ -0,0 +1,268 @@
+/* CPU feature tuning.
+   This file is part of the GNU C Library.
+   Copyright (C) 2017 Free Software Foundation, Inc.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+/* __environ is set after init_cpu_features is called in libc.a.  */
+#ifdef SHARED
+# include <string.h>
+# if HAVE_TUNABLES
+#  define TUNABLE_NAMESPACE x86
+#  include <elf/dl-tunables.h>
+# endif
+# include <cpu-features.h>
+# include <ldsodefs.h>
+
+# define CHECK_GLIBC_IFUNC_CPU_OFF(cpu_features, name)			\
+  if (!memcmp (n, #name, sizeof (#name) - 1))				\
+    {									\
+      cpu_features->cpuid[index_cpu_##name].reg_##name			\
+	&= ~bit_cpu_##name;						\
+      break;								\
+    }
+
+/* Disable an ARCH feature NAME.  We don't enable an ARCH feature which
+   isn't available.  */
+# define CHECK_GLIBC_IFUNC_ARCH_OFF(cpu_features, name)			\
+  if (!memcmp (n, #name, sizeof (#name) - 1))				\
+    {									\
+      cpu_features->feature[index_arch_##name]				\
+	&= ~bit_arch_##name;						\
+      break;								\
+    }
+
+/* Enable/disable an ARCH feature NAME.  */
+# define CHECK_GLIBC_IFUNC_ARCH_BOTH(cpu_features, name, disable)	\
+  if (!memcmp (n, #name, sizeof (#name) - 1))				\
+    {									\
+      if (disable)							\
+	cpu_features->feature[index_arch_##name]			\
+	  &= ~bit_arch_##name;						\
+      else								\
+	cpu_features->feature[index_arch_##name]			\
+	  |= bit_arch_##name;						\
+      break;								\
+    }
+
+/* Enable/disable an ARCH feature NAME.  Enable an ARCH feature only
+   if the ARCH feature NEED is also enabled.  */
+# define CHECK_GLIBC_IFUNC_ARCH_NEED_ARCH_BOTH(cpu_features, name,	\
+					       need, disable)		\
+  if (!memcmp (n, #name, sizeof (#name) - 1))				\
+    {									\
+      if (disable)							\
+	cpu_features->feature[index_arch_##name]			\
+	  &= ~bit_arch_##name;						\
+      else if (CPU_FEATURES_ARCH_P (cpu_features, need))		\
+	cpu_features->feature[index_arch_##name]			\
+	  |= bit_arch_##name;						\
+      break;								\
+    }
+
+/* Enable/disable an ARCH feature NAME.  Enable an ARCH feature only
+   if the CPU feature NEED is also enabled.  */
+# define CHECK_GLIBC_IFUNC_ARCH_NEED_CPU_BOTH(cpu_features, name,	\
+					      need, disable)		\
+  if (!memcmp (n, #name, sizeof (#name) - 1))				\
+    {									\
+      if (disable)							\
+	cpu_features->feature[index_arch_##name]			\
+	  &= ~bit_arch_##name;						\
+      else if (CPU_FEATURES_CPU_P (cpu_features, need))			\
+	cpu_features->feature[index_arch_##name]			\
+	  |= bit_arch_##name;						\
+      break;								\
+    }
+
+# if HAVE_TUNABLES
+static
+# else
+attribute_hidden
+# endif
+void
+set_ifunc (const char *p)
+{
+  /* The current IFUNC selection is based on microbenchmarks in glibc.
+     It should give the best performance for most workloads.  But other
+     choices may have better performance for a particular workload or on
+     the hardware which wasn't available when the selection was made.
+     The environment variable, GLIBC_IFUNC=-xxx,yyy,-zzz...., can be
+     used to enable CPU/ARCH feature yyy, disable CPU/ARCH feature yyy
+     and zzz, where the feature name is case-sensitive and has to match
+     the ones in cpu-features.h.  It can be used by glibc developers to
+     tune for a new processor or override the IFUNC selection to improve
+     performance for a particular workload.
+
+     Since all CPU/ARCH features are hardware optimizations without
+     security implication, except for Prefer_MAP_32BIT_EXEC, which can
+     only be disabled, we check GLIBC_IFUNC for programs, including
+     set*id ones.
+
+     NOTE: the IFUNC selection may change over time.  Please check all
+     multiarch implementations when experimenting.  */
+
+  struct cpu_features *cpu_features = &GLRO(dl_x86_cpu_features);
+  const char *end = p + strlen (p);
+  size_t len;
+
+  do
+    {
+      const char *c, *n;
+      bool disable;
+      size_t nl;
+
+      for (c = p; *c != ','; c++)
+	if (c >= end)
+	  break;
+
+      len = c - p;
+      disable = *p == '-';
+      if (disable)
+	{
+	  n = p + 1;
+	  nl = len - 1;
+	}
+      else
+	{
+	  n = p;
+	  nl = len;
+	}
+      switch (nl)
+	{
+	default:
+	  break;
+	case 3:
+	  if (disable)
+	    {
+	      CHECK_GLIBC_IFUNC_CPU_OFF (cpu_features, AVX);
+	      CHECK_GLIBC_IFUNC_CPU_OFF (cpu_features, CX8);
+	      CHECK_GLIBC_IFUNC_CPU_OFF (cpu_features, FMA);
+	      CHECK_GLIBC_IFUNC_CPU_OFF (cpu_features, HTT);
+	      CHECK_GLIBC_IFUNC_CPU_OFF (cpu_features, RTM);
+	    }
+	  break;
+	case 4:
+	  if (disable)
+	    {
+	      CHECK_GLIBC_IFUNC_CPU_OFF (cpu_features, AVX2);
+	      CHECK_GLIBC_IFUNC_CPU_OFF (cpu_features, CMOV);
+	      CHECK_GLIBC_IFUNC_CPU_OFF (cpu_features, ERMS);
+	      CHECK_GLIBC_IFUNC_CPU_OFF (cpu_features, FMA4);
+	      CHECK_GLIBC_IFUNC_CPU_OFF (cpu_features, SSE2);
+	      CHECK_GLIBC_IFUNC_ARCH_OFF (cpu_features, I586);
+	      CHECK_GLIBC_IFUNC_ARCH_OFF (cpu_features, I686);
+	    }
+	  break;
+	case 5:
+	  if (disable)
+	    {
+	      CHECK_GLIBC_IFUNC_CPU_OFF (cpu_features, SSSE3);
+	    }
+	  break;
+	case 6:
+	  if (disable)
+	    {
+	      CHECK_GLIBC_IFUNC_CPU_OFF (cpu_features, SSE4_1);
+	      CHECK_GLIBC_IFUNC_CPU_OFF (cpu_features, SSE4_2);
+	    }
+	  break;
+	case 7:
+	  if (disable)
+	    {
+	      CHECK_GLIBC_IFUNC_CPU_OFF (cpu_features, AVX512F);
+	      CHECK_GLIBC_IFUNC_CPU_OFF (cpu_features, OSXSAVE);
+	    }
+	  break;
+	case 8:
+	  if (disable)
+	    {
+	      CHECK_GLIBC_IFUNC_CPU_OFF (cpu_features, AVX512DQ);
+	      CHECK_GLIBC_IFUNC_CPU_OFF (cpu_features, POPCOUNT);
+	    }
+	  CHECK_GLIBC_IFUNC_ARCH_BOTH (cpu_features, Slow_BSF, disable);
+	  break;
+	case 10:
+	  if (disable)
+	    {
+	      CHECK_GLIBC_IFUNC_ARCH_OFF (cpu_features, AVX_Usable);
+	      CHECK_GLIBC_IFUNC_ARCH_OFF (cpu_features, FMA_Usable);
+	    }
+	  break;
+	case 11:
+	  if (disable)
+	    {
+	      CHECK_GLIBC_IFUNC_ARCH_OFF (cpu_features, AVX2_Usable);
+	      CHECK_GLIBC_IFUNC_ARCH_OFF (cpu_features, FMA4_Usable);
+	    }
+	  CHECK_GLIBC_IFUNC_ARCH_BOTH (cpu_features, Prefer_ERMS,
+				       disable);
+	  CHECK_GLIBC_IFUNC_ARCH_NEED_CPU_BOTH (cpu_features,
+						Slow_SSE4_2, SSE4_2,
+						disable);
+	  break;
+	case 13:
+	  if (disable)
+	    {
+	      CHECK_GLIBC_IFUNC_ARCH_OFF (cpu_features, AVX512F_Usable);
+	    }
+	  CHECK_GLIBC_IFUNC_ARCH_NEED_ARCH_BOTH
+	    (cpu_features, AVX_Fast_Unaligned_Load, AVX_Usable, disable);
+	  break;
+	case 15:
+	  if (disable)
+	    {
+	      CHECK_GLIBC_IFUNC_ARCH_OFF (cpu_features, AVX512DQ_Usable);
+	    }
+	  CHECK_GLIBC_IFUNC_ARCH_BOTH (cpu_features, Fast_Rep_String,
+				       disable);
+	  break;
+	case 18:
+	  CHECK_GLIBC_IFUNC_ARCH_BOTH (cpu_features, Fast_Copy_Backward,
+				       disable);
+	  break;
+	case 19:
+	  CHECK_GLIBC_IFUNC_ARCH_BOTH (cpu_features, Fast_Unaligned_Load,
+				       disable);
+	  CHECK_GLIBC_IFUNC_ARCH_BOTH (cpu_features, Fast_Unaligned_Copy,
+				       disable);
+	  break;
+	case 20:
+	  CHECK_GLIBC_IFUNC_ARCH_NEED_ARCH_BOTH
+	    (cpu_features, Prefer_No_VZEROUPPER, AVX_Usable, disable);
+	  break;
+	case 21:
+	  CHECK_GLIBC_IFUNC_ARCH_BOTH (cpu_features,
+				       Prefer_MAP_32BIT_EXEC, disable);
+	  break;
+	case 26:
+	  CHECK_GLIBC_IFUNC_ARCH_NEED_CPU_BOTH
+	    (cpu_features, Prefer_PMINUB_for_stringop, SSE2, disable);
+	  break;
+	}
+      p += len + 1;
+    }
+  while (p < end);
+}
+
+# if HAVE_TUNABLES
+attribute_hidden
+void
+DL_TUNABLE_CALLBACK (set_ifunc) (tunable_val_t *valp)
+{
+  set_ifunc (valp->strval);
+}
+# endif
+#endif
diff --git a/sysdeps/x86/dl-tunables.list b/sysdeps/x86/dl-tunables.list
new file mode 100644
index 0000000..0c9acc0
--- /dev/null
+++ b/sysdeps/x86/dl-tunables.list
@@ -0,0 +1,9 @@
+glibc {
+  x86 {
+    ifunc {
+      type: STRING
+      env_alias: GLIBC_IFUNC
+      security_level: SXID_IGNORE
+    }
+  }
+}

http://sourceware.org/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=550d7c92cd5cb45e5ead7e69090f904f60cec3b8

commit 550d7c92cd5cb45e5ead7e69090f904f60cec3b8
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Wed May 24 12:34:26 2017 -0700

    Support dl-tunables.list in subdirectories
    
    We can put processor specific tunables in dl-tunables.list under
    sysdeps instead of in elf/dl-tunables.list.
    
    	* Makeconfig ($(common-objpfx)dl-tunable-list.h): Also check
    	dl-tunables.list in subdirectories.

diff --git a/Makeconfig b/Makeconfig
index b494b82..e4eda4b 100644
--- a/Makeconfig
+++ b/Makeconfig
@@ -1127,7 +1127,9 @@ ifneq (no,$(have-tunables))
 before-compile += $(common-objpfx)dl-tunable-list.h
 
 $(common-objpfx)dl-tunable-list.h: $(..)scripts/gen-tunables.awk \
-				   $(..)elf/dl-tunables.list
+				   $(..)elf/dl-tunables.list \
+				   $(wildcard $(subdirs:%=$(..)%/dl-tunables.list)) \
+				   $(wildcard $(sysdirs:%=%/dl-tunables.list))
 	$(AWK) -f $^ > $@.tmp
 	mv $@.tmp $@
 endif

http://sourceware.org/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=121b22afbc4dd1d683dd7ee0eb815f322df93ab9

commit 121b22afbc4dd1d683dd7ee0eb815f322df93ab9
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Wed May 24 12:09:41 2017 -0700

    Mark __tunables_init hidden and avoid PLT
    
    Since __tunables_init is internal to ld.so, we should mark it hidden
    to avoid PLT.  We should also avoid PLT when calling __tunable_set_val
    within ld.so.
    
    	* elf/dl-tunables.c (__tunables_init): Mark hidden.
    	(__rtld_tunable_set_val): Add a hidden alias for
    	__tunable_set_val.
    	* elf/dl-tunables.h (__tunables_init): Mark hidden.
    	(__rtld_tunable_set_val): New.
    	(DL_TUNABLE_SET_VAL): Likewise.
    	(TUNABLE_SET_VAL): Replace __tunable_set_val with
    	DL_TUNABLE_SET_VAL.
    	(TUNABLE_SET_VAL_WITH_CALLBACK): Likewise.

diff --git a/elf/dl-tunables.c b/elf/dl-tunables.c
index 8d72e26..d6f3309 100644
--- a/elf/dl-tunables.c
+++ b/elf/dl-tunables.c
@@ -344,6 +344,7 @@ maybe_enable_malloc_check (void)
 /* Initialize the tunables list from the environment.  For now we only use the
    ENV_ALIAS to find values.  Later we will also use the tunable names to find
    values.  */
+__attribute__ ((visibility ("hidden")))
 void
 __tunables_init (char **envp)
 {
@@ -423,6 +424,10 @@ __tunables_init (char **envp)
     }
 }
 
+extern void __rtld_tunable_set_val (tunable_id_t, void *,
+				    tunable_callback_t)
+  __attribute__ ((alias ("__tunable_set_val"), visibility ("hidden")));
+
 /* Set the tunable value.  This is called by the module that the tunable exists
    in. */
 void
diff --git a/elf/dl-tunables.h b/elf/dl-tunables.h
index f33adfb..713a42e 100644
--- a/elf/dl-tunables.h
+++ b/elf/dl-tunables.h
@@ -66,14 +66,24 @@ typedef struct _tunable tunable_t;
 
 # include "dl-tunable-list.h"
 
-extern void __tunables_init (char **);
+extern void __tunables_init (char **)
+  __attribute__ ((visibility ("hidden")));
 extern void __tunable_set_val (tunable_id_t, void *, tunable_callback_t);
+extern void __rtld_tunable_set_val (tunable_id_t, void *, tunable_callback_t)
+  __attribute__ ((visibility ("hidden")));
+
+/* Avoid PLT when calling __tunable_set_val within ld.so.  */
+#if IS_IN (rtld)
+# define DL_TUNABLE_SET_VAL	__rtld_tunable_set_val
+#else
+# define DL_TUNABLE_SET_VAL	__tunable_set_val
+#endif
 
 /* Check if the tunable has been set to a non-default value and if it is, copy
    it over into __VAL.  */
 # define TUNABLE_SET_VAL(__id,__val) \
 ({									      \
-  __tunable_set_val							      \
+  DL_TUNABLE_SET_VAL							      \
    (TUNABLE_ENUM_NAME (TOP_NAMESPACE, TUNABLE_NAMESPACE, __id), (__val),      \
     NULL);								      \
 })
@@ -81,7 +91,7 @@ extern void __tunable_set_val (tunable_id_t, void *, tunable_callback_t);
 /* Same as TUNABLE_SET_VAL, but also call the callback function __CB.  */
 # define TUNABLE_SET_VAL_WITH_CALLBACK(__id,__val,__cb) \
 ({									      \
-  __tunable_set_val							      \
+  DL_TUNABLE_SET_VAL							      \
    (TUNABLE_ENUM_NAME (TOP_NAMESPACE, TUNABLE_NAMESPACE, __id), (__val),      \
     DL_TUNABLE_CALLBACK (__cb));					      \
 })

http://sourceware.org/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=6d145adf93f8185712856f3baddbf3aa8abc11fc

commit 6d145adf93f8185712856f3baddbf3aa8abc11fc
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Wed May 24 13:05:25 2017 -0700

    x86: Don't use dl_x86_cpu_features in cacheinfo.c
    
    Since cpu_features is available, use it instead of dl_x86_cpu_features.
    
    	* sysdeps/x86/cacheinfo.c (intel_check_word): Accept cpu_features
    	and use it instead of dl_x86_cpu_features.
    	(handle_intel): Replace maxidx with cpu_features.  Pass
    	cpu_features to intel_check_word.
    	(__cache_sysconf): Pass cpu_features to handle_intel.
    	(init_cacheinfo): Likewise.  Use cpu_features instead of
    	dl_x86_cpu_features.

diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c
index 321fbb6..a46dd4d 100644
--- a/sysdeps/x86/cacheinfo.c
+++ b/sysdeps/x86/cacheinfo.c
@@ -126,7 +126,8 @@ intel_02_known_compare (const void *p1, const void *p2)
 static long int
 __attribute__ ((noinline))
 intel_check_word (int name, unsigned int value, bool *has_level_2,
-		  bool *no_level_2_or_3)
+		  bool *no_level_2_or_3,
+		  const struct cpu_features *cpu_features)
 {
   if ((value & 0x80000000) != 0)
     /* The register value is reserved.  */
@@ -204,8 +205,8 @@ intel_check_word (int name, unsigned int value, bool *has_level_2,
 	      /* Intel reused this value.  For family 15, model 6 it
 		 specifies the 3rd level cache.  Otherwise the 2nd
 		 level cache.  */
-	      unsigned int family = GLRO(dl_x86_cpu_features).family;
-	      unsigned int model = GLRO(dl_x86_cpu_features).model;
+	      unsigned int family = cpu_features->family;
+	      unsigned int model = cpu_features->model;
 
 	      if (family == 15 && model == 6)
 		{
@@ -255,8 +256,10 @@ intel_check_word (int name, unsigned int value, bool *has_level_2,
 
 
 static long int __attribute__ ((noinline))
-handle_intel (int name, unsigned int maxidx)
+handle_intel (int name, const struct cpu_features *cpu_features)
 {
+  unsigned int maxidx = cpu_features->max_cpuid;
+
   /* Return -1 for older CPUs.  */
   if (maxidx < 2)
     return -1;
@@ -287,19 +290,23 @@ handle_intel (int name, unsigned int maxidx)
 	}
 
       /* Process the individual registers' value.  */
-      result = intel_check_word (name, eax, &has_level_2, &no_level_2_or_3);
+      result = intel_check_word (name, eax, &has_level_2,
+				 &no_level_2_or_3, cpu_features);
       if (result != 0)
 	return result;
 
-      result = intel_check_word (name, ebx, &has_level_2, &no_level_2_or_3);
+      result = intel_check_word (name, ebx, &has_level_2,
+				 &no_level_2_or_3, cpu_features);
       if (result != 0)
 	return result;
 
-      result = intel_check_word (name, ecx, &has_level_2, &no_level_2_or_3);
+      result = intel_check_word (name, ecx, &has_level_2,
+				 &no_level_2_or_3, cpu_features);
       if (result != 0)
 	return result;
 
-      result = intel_check_word (name, edx, &has_level_2, &no_level_2_or_3);
+      result = intel_check_word (name, edx, &has_level_2,
+				 &no_level_2_or_3, cpu_features);
       if (result != 0)
 	return result;
     }
@@ -437,7 +444,7 @@ __cache_sysconf (int name)
   const struct cpu_features *cpu_features = __get_cpu_features ();
 
   if (cpu_features->kind == arch_kind_intel)
-    return handle_intel (name, cpu_features->max_cpuid);
+    return handle_intel (name, cpu_features);
 
   if (cpu_features->kind == arch_kind_amd)
     return handle_amd (name);
@@ -494,14 +501,14 @@ init_cacheinfo (void)
 
   if (cpu_features->kind == arch_kind_intel)
     {
-      data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, max_cpuid);
+      data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, cpu_features);
 
-      long int core = handle_intel (_SC_LEVEL2_CACHE_SIZE, max_cpuid);
+      long int core = handle_intel (_SC_LEVEL2_CACHE_SIZE, cpu_features);
       bool inclusive_cache = true;
 
       /* Try L3 first.  */
       level  = 3;
-      shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, max_cpuid);
+      shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, cpu_features);
 
       /* Number of logical processors sharing L2 cache.  */
       int threads_l2;
@@ -531,8 +538,8 @@ init_cacheinfo (void)
 	     highest cache level.  */
 	  if (max_cpuid >= 4)
 	    {
-	      unsigned int family = GLRO(dl_x86_cpu_features).family;
-	      unsigned int model = GLRO(dl_x86_cpu_features).model;
+	      unsigned int family = cpu_features->family;
+	      unsigned int model = cpu_features->model;
 
 	      int i = 0;
 
@@ -675,7 +682,7 @@ intel_bug_no_cache_info:
 		 level.  */
 
 	      threads
-		= ((GLRO(dl_x86_cpu_features).cpuid[COMMON_CPUID_INDEX_1].ebx
+		= ((cpu_features->cpuid[COMMON_CPUID_INDEX_1].ebx
 		    >> 16) & 0xff);
 	    }
 

http://sourceware.org/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=3218f328d840ffa69198f87a81ca88a8102205b5

commit 3218f328d840ffa69198f87a81ca88a8102205b5
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Tue May 23 20:22:13 2017 -0700

    x86: Add cache info to cpu_features
    
    This patch adds cache info to cpu_features to support tunables for both
    cache info as well as CPU features in a single x86 namespace.  Since
    init_cacheinfo is in libc.so and cpu_features is in ld.so, cache info
    and CPU features must be in a place for tunables.
    
    	* sysdeps/x86/cacheinfo.c (init_cacheinfo): Use data_size,
    	shared_size and non_temporal_threshold from cpu_features if
    	they aren't zero.
    	* sysdeps/x86/cpu-features.h (cache_info): New.
    	(cpu_features): Add cache.

diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c
index 12ffeef..321fbb6 100644
--- a/sysdeps/x86/cacheinfo.c
+++ b/sysdeps/x86/cacheinfo.c
@@ -745,6 +745,9 @@ intel_bug_no_cache_info:
 #endif
     }
 
+  if (cpu_features->cache.data_size != 0)
+    data = cpu_features->cache.data_size;
+
   if (data > 0)
     {
       __x86_raw_data_cache_size_half = data / 2;
@@ -755,6 +758,9 @@ intel_bug_no_cache_info:
       __x86_data_cache_size = data;
     }
 
+  if (cpu_features->cache.shared_size != 0)
+    shared = cpu_features->cache.shared_size;
+
   if (shared > 0)
     {
       __x86_raw_shared_cache_size_half = shared / 2;
@@ -768,7 +774,10 @@ intel_bug_no_cache_info:
   /* The large memcpy micro benchmark in glibc shows that 6 times of
      shared cache size is the approximate value above which non-temporal
      store becomes faster.  */
-  __x86_shared_non_temporal_threshold = __x86_shared_cache_size * 6;
+  __x86_shared_non_temporal_threshold
+    = (cpu_features->cache.non_temporal_threshold != 0
+       ? cpu_features->cache.non_temporal_threshold
+       : __x86_shared_cache_size * 6);
 }
 
 #endif
diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h
index 31c7c80..f428dca 100644
--- a/sysdeps/x86/cpu-features.h
+++ b/sysdeps/x86/cpu-features.h
@@ -185,6 +185,18 @@
 
 #else	/* __ASSEMBLER__ */
 
+struct cache_info
+{
+  /* Data cache size for use in memory and string routines, typically
+     L1 size.  */
+  long int data_size;
+  /* Shared cache size for use in memory and string routines, typically
+     L2 or L3 size.  */
+  long int shared_size;
+  /* Threshold to use non temporal store.  */
+  long int non_temporal_threshold;
+};
+
 enum
   {
     COMMON_CPUID_INDEX_1 = 0,
@@ -214,6 +226,7 @@ struct cpu_features
   unsigned int family;
   unsigned int model;
   unsigned int feature[FEATURE_INDEX_MAX];
+  struct cache_info cache;
 };
 
 /* Used from outside of glibc to get access to the CPU features

-----------------------------------------------------------------------


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