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GNU C Library master sources branch hjl/cacheinfo/master created. glibc-2.25-364-g79bef76


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The branch, hjl/cacheinfo/master has been created
        at  79bef76c28ea94f09b76846575c88c4e73ead2da (commit)

- Log -----------------------------------------------------------------
http://sourceware.org/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=79bef76c28ea94f09b76846575c88c4e73ead2da

commit 79bef76c28ea94f09b76846575c88c4e73ead2da
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Tue May 23 20:22:13 2017 -0700

    x86: Add cache info to cpu_features
    
    This patch adds cache info to cpu_features to support tunables for both
    cache info as well as CPU features in a single x86 namespace.  Since
    init_cacheinfo is in libc.so and cpu_features is in ld.so, cache info
    and CPU features must be in a place for tunables.
    
    	* sysdeps/x86/cacheinfo.c (init_cacheinfo): Use data_size,
    	shared_size and non_temporal_threshold from cpu_features if
    	they aren't not zero.
    	* sysdeps/x86/cpu-features.h (cache_info): New.
    	(cpu_features): Add cache.

diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c
index 12ffeef..321fbb6 100644
--- a/sysdeps/x86/cacheinfo.c
+++ b/sysdeps/x86/cacheinfo.c
@@ -745,6 +745,9 @@ intel_bug_no_cache_info:
 #endif
     }
 
+  if (cpu_features->cache.data_size != 0)
+    data = cpu_features->cache.data_size;
+
   if (data > 0)
     {
       __x86_raw_data_cache_size_half = data / 2;
@@ -755,6 +758,9 @@ intel_bug_no_cache_info:
       __x86_data_cache_size = data;
     }
 
+  if (cpu_features->cache.shared_size != 0)
+    shared = cpu_features->cache.shared_size;
+
   if (shared > 0)
     {
       __x86_raw_shared_cache_size_half = shared / 2;
@@ -768,7 +774,10 @@ intel_bug_no_cache_info:
   /* The large memcpy micro benchmark in glibc shows that 6 times of
      shared cache size is the approximate value above which non-temporal
      store becomes faster.  */
-  __x86_shared_non_temporal_threshold = __x86_shared_cache_size * 6;
+  __x86_shared_non_temporal_threshold
+    = (cpu_features->cache.non_temporal_threshold != 0
+       ? cpu_features->cache.non_temporal_threshold
+       : __x86_shared_cache_size * 6);
 }
 
 #endif
diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h
index 31c7c80..f428dca 100644
--- a/sysdeps/x86/cpu-features.h
+++ b/sysdeps/x86/cpu-features.h
@@ -185,6 +185,18 @@
 
 #else	/* __ASSEMBLER__ */
 
+struct cache_info
+{
+  /* Data cache size for use in memory and string routines, typically
+     L1 size.  */
+  long int data_size;
+  /* Shared cache size for use in memory and string routines, typically
+     L2 or L3 size.  */
+  long int shared_size;
+  /* Threshold to use non temporal store.  */
+  long int non_temporal_threshold;
+};
+
 enum
   {
     COMMON_CPUID_INDEX_1 = 0,
@@ -214,6 +226,7 @@ struct cpu_features
   unsigned int family;
   unsigned int model;
   unsigned int feature[FEATURE_INDEX_MAX];
+  struct cache_info cache;
 };
 
 /* Used from outside of glibc to get access to the CPU features

http://sourceware.org/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=91be4dced0570c0408beb7618d9a6c15376457e6

commit 91be4dced0570c0408beb7618d9a6c15376457e6
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Tue May 23 20:10:04 2017 -0700

    x86: Don't include cacheinfo.c in ld.so
    
    Since cacheinfo.c isn't used by ld.so, there is no need to include it
    in ld.so.
    
    	* sysdeps/x86/cacheinfo.c: Skip if not in libc.

diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c
index 4594a2f..12ffeef 100644
--- a/sysdeps/x86/cacheinfo.c
+++ b/sysdeps/x86/cacheinfo.c
@@ -16,6 +16,8 @@
    License along with the GNU C Library; if not, see
    <http://www.gnu.org/licenses/>.  */
 
+#if IS_IN (libc)
+
 #include <assert.h>
 #include <stdbool.h>
 #include <stdlib.h>
@@ -768,3 +770,5 @@ intel_bug_no_cache_info:
      store becomes faster.  */
   __x86_shared_non_temporal_threshold = __x86_shared_cache_size * 6;
 }
+
+#endif

http://sourceware.org/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=3dd063a2acbe05bc9db2b49459a4df883a51f5d8

commit 3dd063a2acbe05bc9db2b49459a4df883a51f5d8
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Tue May 23 19:56:43 2017 -0700

    x86: Use __get_cpu_features to get cpu_features
    
    Remove is_intel, is_amd and max_cpuid macros.  Use __get_cpu_features
    to get cpu_features instead.
    
    	* sysdeps/x86/cacheinfo.c (is_intel): Removed.
    	(is_amd): Likewise.
    	(max_cpuid): Likewise.
    	(__cache_sysconf): Use __get_cpu_features to get cpu_features.
    	(init_cacheinfo): Likewise.

diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c
index 1ccbe41..4594a2f 100644
--- a/sysdeps/x86/cacheinfo.c
+++ b/sysdeps/x86/cacheinfo.c
@@ -23,10 +23,6 @@
 #include <cpuid.h>
 #include <init-arch.h>
 
-#define is_intel GLRO(dl_x86_cpu_features).kind == arch_kind_intel
-#define is_amd GLRO(dl_x86_cpu_features).kind == arch_kind_amd
-#define max_cpuid GLRO(dl_x86_cpu_features).max_cpuid
-
 static const struct intel_02_cache_info
 {
   unsigned char idx;
@@ -436,10 +432,12 @@ long int
 attribute_hidden
 __cache_sysconf (int name)
 {
-  if (is_intel)
-    return handle_intel (name, max_cpuid);
+  const struct cpu_features *cpu_features = __get_cpu_features ();
+
+  if (cpu_features->kind == arch_kind_intel)
+    return handle_intel (name, cpu_features->max_cpuid);
 
-  if (is_amd)
+  if (cpu_features->kind == arch_kind_amd)
     return handle_amd (name);
 
   // XXX Fill in more vendors.
@@ -489,8 +487,10 @@ init_cacheinfo (void)
   long int shared = -1;
   unsigned int level;
   unsigned int threads = 0;
+  const struct cpu_features *cpu_features = __get_cpu_features ();
+  int max_cpuid = cpu_features->max_cpuid;
 
-  if (is_intel)
+  if (cpu_features->kind == arch_kind_intel)
     {
       data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, max_cpuid);
 
@@ -691,8 +691,7 @@ intel_bug_no_cache_info:
 	  shared += core;
 	}
     }
-  /* This spells out "AuthenticAMD".  */
-  else if (is_amd)
+  else if (cpu_features->kind == arch_kind_amd)
     {
       data   = handle_amd (_SC_LEVEL1_DCACHE_SIZE);
       long int core = handle_amd (_SC_LEVEL2_CACHE_SIZE);

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