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GNU C Library master sources branch hjl/cache/master created. glibc-2.23-327-g3313be3


This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "GNU C Library master sources".

The branch, hjl/cache/master has been created
        at  3313be3042190582e90bc67b953aef1d36bae7a9 (commit)

- Log -----------------------------------------------------------------
http://sourceware.org/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=3313be3042190582e90bc67b953aef1d36bae7a9

commit 3313be3042190582e90bc67b953aef1d36bae7a9
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Sat May 14 06:36:53 2016 -0700

    Check HTT

diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c
index 6fe41be..8b187c4 100644
--- a/sysdeps/x86/cacheinfo.c
+++ b/sysdeps/x86/cacheinfo.c
@@ -512,6 +512,9 @@ init_cacheinfo (void)
       else
 	logical_threads_l2 = 0;
 
+      if (!HAS_CPU_FEATURE (HTT))
+	goto intel_no_threads;
+
       /* Figure out the number of logical threads that share the
 	 highest cache level.  */
       if (max_cpuid >= 4)
@@ -618,6 +621,7 @@ init_cacheinfo (void)
 		>> 16) & 0xff);
 	}
 
+intel_no_threads:
       /* Cap usage of highest cache level to the number of supported
 	 threads.  */
       if (shared > 0 && threads > 0)
diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h
index 9529d61..2bd9371 100644
--- a/sysdeps/x86/cpu-features.h
+++ b/sysdeps/x86/cpu-features.h
@@ -51,6 +51,7 @@
 #define bit_cpu_POPCOUNT	(1 << 23)
 #define bit_cpu_FMA		(1 << 12)
 #define bit_cpu_FMA4		(1 << 16)
+#define bit_cpu_HTT		(1 << 28)
 
 /* COMMON_CPUID_INDEX_7.  */
 #define bit_cpu_ERMS		(1 << 9)
@@ -235,6 +236,7 @@ extern const struct cpu_features *__get_cpu_features (void)
 # define index_cpu_FMA4		COMMON_CPUID_INDEX_80000001
 # define index_cpu_POPCOUNT	COMMON_CPUID_INDEX_1
 # define index_cpu_OSXSAVE	COMMON_CPUID_INDEX_1
+# define index_cpu_HTT		COMMON_CPUID_INDEX_1
 
 # define reg_CX8		edx
 # define reg_CMOV		edx
@@ -252,6 +254,7 @@ extern const struct cpu_features *__get_cpu_features (void)
 # define reg_FMA4		ecx
 # define reg_POPCOUNT		ecx
 # define reg_OSXSAVE		ecx
+# define reg_HTT		edx
 
 # define index_arch_Fast_Rep_String	FEATURE_INDEX_1
 # define index_arch_Fast_Copy_Backward	FEATURE_INDEX_1

http://sourceware.org/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=2fc466a09dc25be636d711b41113bd1bd8c02ec6

commit 2fc466a09dc25be636d711b41113bd1bd8c02ec6
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Fri May 13 13:26:37 2016 -0700

    Count number of logical processors sharing L2 cache
    
    For Intel processors, we should count number of available logical
    processors sharing L2 cache for non-inclusive L2 and L3 caches.
    
    	* sysdeps/x86/cacheinfo.c (init_cacheinfo): Count number of
    	available logical processors sharing L2 cache for Intel
    	processors.

diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c
index 8408624..6fe41be 100644
--- a/sysdeps/x86/cacheinfo.c
+++ b/sysdeps/x86/cacheinfo.c
@@ -499,12 +499,18 @@ init_cacheinfo (void)
       level  = 3;
       shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, max_cpuid);
 
+      /* Number of logical processors sharing L2 cache.  */
+      int logical_threads_l2;
+
       if (shared <= 0)
 	{
 	  /* Try L2 otherwise.  */
 	  level  = 2;
 	  shared = core;
+	  logical_threads_l2 = -1;
 	}
+      else
+	logical_threads_l2 = 0;
 
       /* Figure out the number of logical threads that share the
 	 highest cache level.  */
@@ -526,6 +532,11 @@ init_cacheinfo (void)
 		 assume there is no such information.  */
 	      if ((eax & 0x1f) == 0)
 		goto intel_bug_no_cache_info;
+
+	      /* Get maximum number of logical processors sharing L2
+		 cache.  */
+	      if (logical_threads_l2 == 0 && ((eax >> 5) & 0x7) == 2)
+		logical_threads_l2 = (eax >> 14) & 0x3ff;
 	    }
 	  while (((eax >> 5) & 0x7) != level);
 
@@ -551,6 +562,19 @@ init_cacheinfo (void)
 		  int type = ecx & 0xff0;
 		  if (shipped == 0 || type == 0)
 		    break;
+		  else if (type == 0x100)
+		    {
+		      if (logical_threads_l2 > 0)
+			{
+			  int count_mask;
+
+			  /* Compute count mask.  */
+			  asm ("bsr %1, %0"
+			       : "=r" (count_mask) : "g" (threads));
+			  count_mask = ~(-1 << (count_mask + 1));
+			  logical_threads_l2 = (shipped - 1) & count_mask;
+			}
+		    }
 		  else if (type == 0x200)
 		    {
 		      int count_mask;
@@ -601,7 +625,11 @@ init_cacheinfo (void)
 
       /* Account for non-inclusive L2 and L3 caches.  */
       if (level == 3 && !inclusive_cache)
-	shared += core;
+	{
+	  if (logical_threads_l2 > 0)
+	    core /= (logical_threads_l2 + 1);
+	  shared += core;
+	}
     }
   /* This spells out "AuthenticAMD".  */
   else if (is_amd)

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