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GNU C Library master sources branch master updated. glibc-2.23-321-g9e4ec3e
- From: hjl at sourceware dot org
- To: glibc-cvs at sourceware dot org
- Date: 13 May 2016 14:39:05 -0000
- Subject: GNU C Library master sources branch master updated. glibc-2.23-321-g9e4ec3e
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- Log -----------------------------------------------------------------
http://sourceware.org/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=9e4ec3e81614164314bffe648e9446f17adc5fb7
commit 9e4ec3e81614164314bffe648e9446f17adc5fb7
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Fri May 13 07:18:25 2016 -0700
Support non-inclusive caches on Intel processors
* sysdeps/x86/cacheinfo.c (init_cacheinfo): Check and support
non-inclusive caches on Intel processors.
diff --git a/ChangeLog b/ChangeLog
index 1f8db94..05d0fe7 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,8 @@
+2016-05-13 H.J. Lu <hongjiu.lu@intel.com>
+
+ * sysdeps/x86/cacheinfo.c (init_cacheinfo): Check and support
+ non-inclusive caches on Intel processors.
+
2016-05-13 Florian Weimer <fweimer@redhat.com>
* malloc/malloc.c (dumped_main_arena_start)
diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c
index 143b333..8408624 100644
--- a/sysdeps/x86/cacheinfo.c
+++ b/sysdeps/x86/cacheinfo.c
@@ -492,6 +492,9 @@ init_cacheinfo (void)
{
data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, max_cpuid);
+ long int core = handle_intel (_SC_LEVEL2_CACHE_SIZE, max_cpuid);
+ bool inclusive_cache = true;
+
/* Try L3 first. */
level = 3;
shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, max_cpuid);
@@ -500,7 +503,7 @@ init_cacheinfo (void)
{
/* Try L2 otherwise. */
level = 2;
- shared = handle_intel (_SC_LEVEL2_CACHE_SIZE, max_cpuid);
+ shared = core;
}
/* Figure out the number of logical threads that share the
@@ -526,6 +529,9 @@ init_cacheinfo (void)
}
while (((eax >> 5) & 0x7) != level);
+ /* Check if cache is inclusive of lower cache levels. */
+ inclusive_cache = (edx & 0x2) != 0;
+
threads = (eax >> 14) & 0x3ff;
/* If max_cpuid >= 11, THREADS is the maximum number of
@@ -592,6 +598,10 @@ init_cacheinfo (void)
threads. */
if (shared > 0 && threads > 0)
shared /= threads;
+
+ /* Account for non-inclusive L2 and L3 caches. */
+ if (level == 3 && !inclusive_cache)
+ shared += core;
}
/* This spells out "AuthenticAMD". */
else if (is_amd)
-----------------------------------------------------------------------
Summary of changes:
ChangeLog | 5 +++++
sysdeps/x86/cacheinfo.c | 12 +++++++++++-
2 files changed, 16 insertions(+), 1 deletions(-)
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