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[Bug libc/18185] Wrong processor count for L2 cache sharing on Silvermont and Knights Landing
- From: "hjl.tools at gmail dot com" <sourceware-bugzilla at sourceware dot org>
- To: glibc-bugs at sourceware dot org
- Date: Fri, 20 May 2016 21:06:19 +0000
- Subject: [Bug libc/18185] Wrong processor count for L2 cache sharing on Silvermont and Knights Landing
- Auto-submitted: auto-generated
- References: <bug-18185-131 at http dot sourceware dot org/bugzilla/>
https://sourceware.org/bugzilla/show_bug.cgi?id=18185
H.J. Lu <hjl.tools at gmail dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|RESOLVED |REOPENED
Resolution|FIXED |---
--- Comment #3 from H.J. Lu <hjl.tools at gmail dot com> ---
It is incorrect for Knights Landing, which has 4 threads per core:
https://en.wikipedia.org/wiki/Xeon_Phi#Knights_Landing
So L2 cache is shared by 2 cores (8 threads).
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