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[Bug string/19881] Improve x86-64 memset


https://sourceware.org/bugzilla/show_bug.cgi?id=19881

--- Comment #6 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot gnu.org> ---
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The branch, hjl/erms/ifunc has been created
        at  e129704237c4ffb5f284dd6d1e3ed638cac3bf02 (commit)

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https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=e129704237c4ffb5f284dd6d1e3ed638cac3bf02

commit e129704237c4ffb5f284dd6d1e3ed638cac3bf02
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Thu Mar 31 18:35:16 2016 -0700

    memmove.S

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=4ec426a6026c1f96f9db56d577e64b75c3e95f4f

commit 4ec426a6026c1f96f9db56d577e64b75c3e95f4f
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Thu Mar 31 18:33:51 2016 -0700

    Remove old GPR, SSE2 and AVX2 memcpy/memmove

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=54a3f917fc4763257ac9d085ce6e1a2b618ca0d3

commit 54a3f917fc4763257ac9d085ce6e1a2b618ca0d3
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Thu Mar 31 16:09:24 2016 -0700

    Use SSE2 memmove by default

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=22ba9213b9e74721847309b71b08d0f524f353e7

commit 22ba9213b9e74721847309b71b08d0f524f353e7
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Thu Mar 31 12:46:57 2016 -0700

    No AVX memmove in rtld

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=36e5b7a18c109faa172e0d78cd061d1d2824060c

commit 36e5b7a18c109faa172e0d78cd061d1d2824060c
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Thu Mar 31 10:42:30 2016 -0700

    X86-64: Remove the previous SSE2/AVX2 memsets

    Since the new SSE2/AVX2 memsets are faster than the previous ones, we
    can remove the previous SSE2/AVX2 memsets and replace them with the
    new ones.

    No change in IFUNC selection if SSE2 and AVX2 memsets weren't used
    before.  If SSE2 or AVX2 memset was used, the new SSE2 or AVX2 memset
    optimized with Enhanced REP STOSB will be used for processors with
    ERMS.

        [BZ #19881]
        * sysdeps/x86_64/multiarch/memset-sse2-unaligned-erms.S: Folded
        into ...
        * sysdeps/x86_64/memset.S: This.
        (__bzero): Removed.
        (__memset_tail): Likewise.
        (__memset_chk): Likewise.
        (memset): Likewise.
        (MEMSET_CHK_SYMBOL): New. Define only if MEMSET_SYMBOL isn't
        defined.
        (MEMSET_SYMBOL): Define only if MEMSET_SYMBOL isn't defined.
        * sysdeps/x86_64/multiarch/memset-avx2.S: Removed.
        (__memset_zero_constant_len_parameter): Check SHARED instead of
        PIC.
        * sysdeps/x86_64/multiarch/Makefile (sysdep_routines): Remove
        memset-avx2 and memset-sse2-unaligned-erms.
        * sysdeps/x86_64/multiarch/ifunc-impl-list.c
        (__libc_ifunc_impl_list): Remove __memset_chk_sse2,
        __memset_chk_avx2, __memset_sse2 and __memset_avx2_unaligned.
        * sysdeps/x86_64/multiarch/memset-avx2-unaligned-erms.S: Skip
        if not in libc.
        * sysdeps/x86_64/multiarch/memset-avx512-unaligned-erms.S:
        Likewise.
        * sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S
        (MEMSET_CHK_SYMBOL): New.  Define if not defined.
        (__bzero): Check VEC_SIZE == 16 instead of USE_MULTIARCH.
        Replace MEMSET_SYMBOL with MEMSET_CHK_SYMBOL on __memset_chk
        symbols.
        Properly check USE_MULTIARCH on __memset symbols.
        * sysdeps/x86_64/multiarch/memset.S (memset): Replace
        __memset_sse2 and __memset_avx2 with __memset_sse2_unaligned
        and __memset_avx2_unaligned.  Use __memset_sse2_unaligned_erms
        or __memset_avx2_unaligned_erms if processor has ERMS.
        (memset): Removed.
        (__memset_chk): Likewise.
        (MEMSET_SYMBOL): New.
        (libc_hidden_builtin_def): Replace __memset_sse2 with
        __memset_sse2_unaligned.
        * sysdeps/x86_64/multiarch/memset_chk.S (__memset_chk): Replace
        __memset_chk_sse2 and __memset_chk_avx2 with
        __memset_chk_sse2_unaligned and __memset_chk_avx2_unaligned_erms.
        Use __memset_chk_sse2_unaligned_erms or
        __memset_chk_avx2_unaligned_erms if processor has ERMS.

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