This is the mail archive of the
glibc-bugs@sourceware.org
mailing list for the glibc project.
[Bug libc/6816] New: Support for POWER7 VSX registers in *context routines
- From: "cseo at linux dot vnet dot ibm dot com" <sourceware-bugzilla at sourceware dot org>
- To: glibc-bugs at sources dot redhat dot com
- Date: 4 Aug 2008 17:57:28 -0000
- Subject: [Bug libc/6816] New: Support for POWER7 VSX registers in *context routines
- Reply-to: sourceware-bugzilla at sourceware dot org
The POWER7 processor will introduce a new register set called VSX (Vector Scalar
Extension), which consists of 64 128-bit wide registers. The new register layout
is as follows:
VSR doubleword 0 VSR doubleword 1
----------------------------------------------------------------
VSR[0] | FPR[0] | |
----------------------------------------------------------------
VSR[1] | FPR[1] | |
----------------------------------------------------------------
| ... | |
| ... | |
----------------------------------------------------------------
VSR[30] | FPR[30] | |
----------------------------------------------------------------
VSR[31] | FPR[31] | |
----------------------------------------------------------------
VSR[32] | FPR[32] VR[0] |
----------------------------------------------------------------
VSR[33] | FPR[33] VR[1] |
----------------------------------------------------------------
| ... |
| ... |
----------------------------------------------------------------
VSR[62] | FPR[62] VR[30] |
----------------------------------------------------------------
VSR[63] | FPR[63] VR[31] |
----------------------------------------------------------------
The first doubleword of registers VSR[0] to VSR[31] overlap with the current
existing floating point registers FPR[0] to FPR[31], while the registers VSR[32]
to VSR[63] overlap with the current existing vector registers (Altivec/VMX)
VR[0] to VR[31].
The VSX ISA introduces a new set of scalar and SIMD instructions that operate in
all VSR registers. Legacy BFP and DFP instructions operate only on
VSR[0]-VSR[31] doubleword 0, and legacy VMX instructions operate only on
VSR[31]-VSR[63].
Initial support for VSX registers and instructions in binutils was added
recently, providing the instructions required for glibc to save the extended
signal frames, as per discussion in:
http://sourceware.org/ml/binutils/2008-08/msg00016.html
and gcc support is being discussed in
http://gcc.gnu.org/ml/gcc-patches/2008-08/msg00162.html .
In order to maintain backward compatibility with older applications, we propose
extending the ucontext, in a way that the doubleword 1 of VSR[0]-VSR[31] is
appended to the end of the ucontext, after VR[31] (or VSR[63]). In other words,
we propose extending the vmx_reserve array within struct sigcontext, in a way
that the doubleword 1 elements from VSRs 0-31 follow the VRSAVE quadword. Note
that this means doubleword 0 and doubleword 1 of VSR[0]-VSR[31] are not stored
in adjacent memory locations. So, in our proposed approach, we have to use
slightly more complicated code than simple loads and stores to save and restore
the register state from the ucontext. However, it is still possible to
accomplish saving and restoring the entire VSX register state using only 64
stores/loads, as it will be shown shortly in a suggested implementation for this.
--
Summary: Support for POWER7 VSX registers in *context routines
Product: glibc
Version: unspecified
Status: NEW
Severity: enhancement
Priority: P2
Component: libc
AssignedTo: drepper at redhat dot com
ReportedBy: cseo at linux dot vnet dot ibm dot com
CC: glibc-bugs at sources dot redhat dot com,rsa at us dot
ibm dot com,sjmunroe at us dot ibm dot com
http://sourceware.org/bugzilla/show_bug.cgi?id=6816
------- You are receiving this mail because: -------
You are on the CC list for the bug, or are watching someone who is.