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[Bug libc/6411] New: PowerPC: Extend fpu fenv operations to operate on 64-bit FPSCR
- From: "rsa at us dot ibm dot com" <sourceware-bugzilla at sourceware dot org>
- To: glibc-bugs at sources dot redhat dot com
- Date: 15 Apr 2008 21:13:51 -0000
- Subject: [Bug libc/6411] New: PowerPC: Extend fpu fenv operations to operate on 64-bit FPSCR
- Reply-to: sourceware-bugzilla at sourceware dot org
The included patch provides the following changes to extend the FPSCR
(floating point status and control register) to 64-bits for PowerPC
POWER6 and POWER6x:
o For PowerPC in general it redefines fpu_control_t from an unsigned
long int to an unsigned long long int so that the entire 64-bit FPSCR on
POWER6 can be saved/restored. On non-POWER6 hardware the high-order
32-bits are simply discarded/ignored for all operations.
It is necessary to change it for all PowerPC because the loader is
built as the default PowerPC arch (i.e. non-POWER6) and uses the
rtld_global_ro struct which contains an fpu_control_t and therefore must
be able to load a libc built for POWER6 or non-POWER6 (which also uses
the rtld_global_ro struct).
Any difference in size of fpu_control_t between the loader and libc
will cause libc to access rtld_global_ro struct members at the wrong
offsets from where the structure was populated by the loader.
The impact is minimal since currently the fpu_control_t is initially
populated from a double anyway and the fpu_control_t type is not used
dynamically in any external function and thus, no symbol versioning is
required.
o Provides a conditional implementation of _FPU_GETCW and _FPU_SETCW
which operate on either the entire 64-bit FPSCR on POWER6[x] or simply
the low-order 32-bits of the fpu_control_t on non-POWER6[x].
o The fegetenv() function will exhibit an undefined high-order word in the
fenv_t. Likewise we leave the high-order 32-bits 'undefined' in the unsigned
long long int fpu_control_t.
o Provides granular control over the high order 32 bits of the FPSCR
that aren't reserved on POWER6[x].
o Provides an overridden sysdeps/powerpc/math/test-fpucw that verifies
that the high-order word is saved to the FPSCR and restored using the
_FPU_[GET|SET]CW macros. It also verifies that there are no deleterious
effects on non-POWER6 systems.
o Provides conditional definitions of the PowerPC fenv helper macros
(fesetenv_register & fegetenv_register) which are used by the fenv
functions to set/get the contents of the FPSCR.
o Provides sysdeps/powerpc/math/test-powerpc-fenv which tests the
high-order word save/restore using the fe[set|get]env_register
functions.
o Replaces the FPSCR restore with a macro which will provide a 64-bit
restore on POWER6 for swapcontext and setcontext.
o Replaces some of the magic number fenv masks in the fenv functions
with a define that better describes what the magic number means.
I successfully executed build and runtime tests (make check) on POWER5
(32-bit FPSCR) as well as POWER6 (64-bit FPSCR).
--
Summary: PowerPC: Extend fpu fenv operations to operate on 64-bit
FPSCR
Product: glibc
Version: unspecified
Status: NEW
Severity: enhancement
Priority: P1
Component: libc
AssignedTo: drepper at redhat dot com
ReportedBy: rsa at us dot ibm dot com
CC: glibc-bugs at sources dot redhat dot com
GCC build triplet: powerpc64-linux
GCC host triplet: powerpc64-linux
GCC target triplet: powerpc64-linux
http://sourceware.org/bugzilla/show_bug.cgi?id=6411
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