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Re: Random SIGILL / SIGSEGV on ARMv7 while debugging ?
- From: Antoine Tremblay <antoine dot tremblay at ericsson dot com>
- To: Antoine Tremblay <antoine dot tremblay at ericsson dot com>
- Cc: Yao Qi <qiyaoltc at gmail dot com>, <gdb at sourceware dot org>, Will Deacon <will dot deacon at arm dot com>
- Date: Wed, 11 May 2016 08:21:37 -0400
- Subject: Re: Random SIGILL / SIGSEGV on ARMv7 while debugging ?
- Authentication-results: sourceware.org; auth=none
- References: <564E136E dot 9090603 at ericsson dot com> <86poz5yr12 dot fsf at gmail dot com> <564F182D dot 2080801 at ericsson dot com> <564F2B42 dot 9000605 at ericsson dot com>
Antoine Tremblay writes:
> On 11/20/2015 07:55 AM, Antoine Tremblay wrote:
>> On 11/20/2015 04:11 AM, Yao Qi wrote:
>
>>> You can turn on debugging output, like "set debug infrun 1" and "set
>>> debug remote 1", and you may find some clues from them.
>
> For reference here is a pastebin of a run with gdb debug on and the
> fault appearing :
>
> http://pastebin.com/nB8gPY2D
After some more investigation, and great help from Will Deacon.
It turns out that theses SIGILL are due to a SoC Hardware bug as
described by Will as such :
So the problem is that A15 has 64-byte I-cache lines and A7 has 32-byte
I-cache lines. That means that if the kernel is doing cache maintenance
on the A15, it will issue an invalidation for each 64 bytes of the region
it wants to invalidate. The A7 will then receive these invalidation
messages, but only invalidate 32 bytes for each one, leaving a bunch of
32-byte holes that didn't get invalidated.
This is an SoC hardware bug. The two cores should report the same line
size (as I mentioned, there's a tie-off on the A15 to make it report
32-byte cachelines)."
The tie-off documentation can be found in the Technical Reference Manual
under "Configuration signals" as IMINLN.
I tested the patch below with an Odroid-UX4 and the problem was fixed.
I have not tested yet with the Firefly RK3288, I'm missing a cable to do
it at the moment...
I will send this to the Odroid team...
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index ee1d805..573db9b 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -82,10 +82,7 @@
* on ARMv7.
*/
.macro icache_line_size, reg, tmp
- mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
- and \tmp, \tmp, #0xf @ cache line size encoding
- mov \reg, #4 @ bytes per word
- mov \reg, \reg, lsl \tmp @ actual cache line size
+ mov \reg, #32 @ hack
.endm