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Hi, I am studying about breakpoint functionality in GDB. My study is local to the MIPS Simulator. While studying the GDB source, I was referring the handling of BREAK instruction. This handling checks for the presence of BREAK instruction in a delay slot and alters the Program Counter. However, this information is overwritten when the CPU registers are saved before triggering a Breakpoint exception. I suspected this would lead to a loss of information regarding the target address of jump/branch instruction. To confirm this, I made a test case and checked the GDB behavior. My assumption is that since the breakpoint is hit after the jump/branch instruction has been executed, the resume should be from the target address. However, it occurred that the GDB resumes from the instruction next to the breakpoint location, which in this case will be the instruction present next to the delay slot instruction. Studying the code, I found that the Program Counter must contain the current instruction address in order to ensure normal processing of breakpoints. If this is altered, the breakpoint functionality in GDB gets affected. However, this seems contrary to my assumption that the resume should be from the target address instead of the next instruction address. Is this assumption correct? Furthermore, I wasn't able to pinpoint any part of the code where the lost information about target address could be restored after the breakpoint has been handled. Please check my understanding. If the above described condition can be handled, please provide me with pointers in the source. The prepared test case is attached. Thanks in advance, Rishi Dixit
Attachment:
delayslotbreak.s
Description: Text document
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