This is a straight bug. The register cache should be marked as invalid
> after the store. What puzzles me is why store.exp doesn't tickle this,
> or is this a hangover from lval_register vs lval_reg_frame_relative?
Where's the invalidation supposed to happen presently? Perhaps I need
to retest.
I don't know if we're talking about the same thing, but this definitely
doesn't happen now. I believe we invalidate the frame cache, not
the current regcache... try it, for example on a remote ARM target:
set debug remote 1
info registers
[see the g packet]
set $r0 = 2
[see the G packet]
info registers
[from the cache, no packets on the wire]