MEMORY{
SRAM_BANK0 : 		org = 0x20001000, l = 0x3000
SRAM_BANK1 : 		org = 0x4000,     l = 0x4000
SRAM_BANK2 : 		org = 0x8000,     l = 0x4000
MMU_SECTION_TABLE :	org = 0x0805C000, l = 0x4000
}

ENTRY (memory) ; 
SECTIONS {
.sram_bank0 0x20001000 :{
_sloadSRAM_BANK0base = . ;
 Startup.o(.memory)
 Main_hello.o(.text)
 TinyRTOS.o(.text)
 ARM720T.o(.text)
 exception.o(.text) 
 *(.text) 
 *(.rodata)
 *(.sdata)
 _eloadSRAM_BANK0base = . ;
 }
_lenimageSRAM_BANK0 = _eloadSRAM_BANK0base - _sloadSRAM_BANK0base ;
_simageSRAM_BANK0base = 0x20001000 ;

.sram_bank1 0x4000 : AT (ADDR(.sram_bank0)+SIZEOF(.sram_bank0)){
  _sloadSRAM_BANK1base = . ;
  *(.data)
  *(.glue_7)
  *(.glue_7t)
  _eloadSRAM_BANK1base = . ;
  }
_lenimageSRAM_BANK1 = _eloadSRAM_BANK1base - _sloadSRAM_BANK1base ;
_simageSRAM_BANK1base = 0x4000 ;

.bss 0x8000 : AT (ADDR(.sram_bank0)+ SIZEOF(.sram_bank0) + SIZEOF(.sram_bank1)){
_sloadSRAM_BANK2base = . ;
__bss_start__ = ABSOLUTE(.) ;
*(.COMMON)
*(.bss) 
__bss_end__ = ABSOLUTE(.);
_eloadSRAM_BANK2base = . ;
}
_lenimageSRAM_BANK2  = _eloadSRAM_BANK2base - _sloadSRAM_BANK2base;
_lenZISRAM_BANK2 = _lenimageSRAM_BANK2; 
_simageSRAM_BANK2base = 0x8000 ;
_simageZISRAM_BANK2base = 0x8000 ;

.mmu_section_table 0x0805C000 : AT (ADDR(.sram_bank0) + SIZEOF(.sram_bank0) + SIZEOF(.sram_bank1) + SIZEOF(.bss) ){
_sloadDRAMbase = . ;
MMU.o(.comm)
_eloadDRAMbase = . ;
} 

_lenimageDRAM = _eloadDRAMbase - _sloadDRAMbase ;
_lenZIDRAM = _lenimageDRAM ;
_simageDRAMbase = 0x0805C000 ;
_simageZIDRAMbase    = _simageDRAMbase ;
}
end = 0xffffffff;