Re: MMX registers on x86?

[jtc@redback.com (J.T. Conklin)]

>>>>> "Jim" == Jim Blandy <jimb@cygnus.com> writes:
>> I know folks are talking about floating point support in gdb, but
>> what about MMX (including 3dnow) registers?
>>
>> In my work with 3dnow, I used as a solution a routine which stored
>> the 8 mmx registers in memory, and I just examined that instead...

> I haven't heard of anyone else working on this.  Write a patch!
> :)

One thing I noticed about the x86 targets is that in many cases the
floating point registers are bolted on the side (obtained with info
float instead of info regs) if they are present at all, instead of
being first class citizens.

This may be a result of the tm-i386.h having NUM_FREG being defined as
0 (8 is commented out), and since most x86 target configs inherit base
definitions from that file, floating point support has been added only
sporadically.  Of the specific targets where floating point support
has been added, it appears that most have added it via the FLOAT_INFO
macro.  

FLOAT_INFO expands to a function that obtains FPU state (sometimes
with a ptrace call, sometimes by frobbing the u area directly, etc.)
and outputs the result.  The x86 float info functions produce nicely
formatted output, especially the FPU control and status words, but at
the expense of being able to set FPU registers within GDB, reading FPU
registers in core dumps, etc.

This is an all-to-easy comment to make now, but I believe what should
have happened is that the tm-i386.h file should have defined the FPU
registers as they are in the processor; and those targets that can't
support the FPU should have been forced to make whatever provisions
necessary to adjust.  It's a bit difficult to make that change now,
since it's hard to tell what targets are going to break because of
the chage.  

	--jtc

-- 
J.T. Conklin
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