[binutils-gdb] [AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.

[sergiodj+buildbot at redhat dot com]

*** TEST RESULTS FOR COMMIT bb515fea4ac30f761c17dec701c95c0b54fabf30 ***

Author: Matthew Wahab <matthew.wahab@arm.com>
Branch: master
Commit: bb515fea4ac30f761c17dec701c95c0b54fabf30

[AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.

ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Adv.SIMD Across Lanes, making them available
when +simd+fp16 is enabled.

The instructions added are: FMAXNMV, FMAXV, FMINNMV and FMINV.

The general form for these instructions is
   <OP> <Hd>, <V>.<T>
   where T is 4h or 8h.

The new instructions valid make uses of the 8H and 4H that were
previously illegal. The patch adjusts a test for illegal uses of vector
types to take this into account.

gas/testsuite/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/advsimd-fp16.d: Update expected output.
	* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes
	instructions.
	* gas/aarch64/illegal.d: Update expected output.
	* gas/aarch64/illegal.s: Replace test for illegal use of 'h'
	specifier.

opcodes/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-tbl.h (QL_XLANES_FP_H): New.
	(aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv,
	fminnmv, fminv to the Adv.SIMD across lanes group.

Change-Id: Ib9a47e867f55e0272c2446eb7e16837503d2f94c