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[PATCH] [AARCH64] Fix decoding of neon memory hint insns
- From: jose dot marchesi at oracle dot com (Jose E. Marchesi)
- To: gdb-patches at sourceware dot org
- Date: Thu, 05 Oct 2017 14:40:03 +0200
- Subject: [PATCH] [AARCH64] Fix decoding of neon memory hint insns
- Authentication-results: sourceware.org; auth=none
Hi guys!
Today I got this error building GDB with the latest svn GCC:
../../gdb/arm-tdep.c: In function ‘int arm_decode_misc_memhint_neon(gdbarch*, uint32_t, regcache*, displaced_step_closure*)’:
../../gdb/arm-tdep.c:6411:52: error: bitwise comparison always evaluates to false [-Werror=tautological-compare]
else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1)
I believe the patch below does the right thing. According to the ARM
ARM, bits 19..16 are 0001 for SETEND and iim1 (where ii is immod and m
is mmod) for CPS.
commit 821015b19fa66f01d707695309486262351e1e5b
Author: Jose E. Marchesi <jose.marchesi@oracle.com>
Date: Thu Oct 5 12:33:19 2017 +0000
gdb: Fix decoding of ARM neon memory hint insns
gdb/ChangeLog:
2017-10-05 Jose E. Marchesi <jose.marchesi@oracle.com>
* arm-tdep.c (arm_decode_misc_memhint_neon): Fix decoding of CPS
and SETEND.
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 2709321..d8569e0 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -6406,9 +6406,9 @@ arm_decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn,
unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7);
unsigned int rn = bits (insn, 16, 19);
- if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0xe) == 0x0)
+ if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0x1) == 0x0)
return arm_copy_unmodified (gdbarch, insn, "cps", dsc);
- else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1)
+ else if (op1 == 0x10 && op2 == 0x0 && (rn & 0x1) == 0x1)
return arm_copy_unmodified (gdbarch, insn, "setend", dsc);
else if ((op1 & 0x60) == 0x20)
return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc);