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[PATCH 1/1] gdb: corelow: make it possible to modify registers for a corefile
- From: Roman Pen <roman dot penyaev at profitbricks dot com>
- To:
- Cc: Roman Pen <roman dot penyaev at profitbricks dot com>, Pedro Alves <palves at redhat dot com>, Daniel Jacobowitz <drow at false dot org>, Jan Kratochvil <jan dot kratochvil at redhat dot com>, gdb-patches at sourceware dot org, Stefan Hajnoczi <stefanha at redhat dot com>, Paolo Bonzini <pbonzini at redhat dot com>
- Date: Tue, 28 Mar 2017 17:29:18 +0200
- Subject: [PATCH 1/1] gdb: corelow: make it possible to modify registers for a corefile
- Authentication-results: sourceware.org; auth=none
This change eases debugging of a jmp_buf (setjmp()) and user contexts
(makecontext()), which are highly used in QEMU project as a part of
coroutines.
This change allows setting registers for a corefile, thus it makes
possible to investigate backtraces of preemted contexts just setting
correct registers taken from jmp_buf or ucontext_t structures. Before
it was possible to debug only live processes.
This patch caches all register on a first attempt to modify register
'(gdb) set $REG = ADDR' and then cached copy is always returned from
get_core_registers().
No harmful impact on previous behaviour is expected, since it was not
allowed to set registers for a corefile, obviously nobody did that
before. If registers are not cached (default behaviour) old execution
path will be executed and registers will be reread.
Signed-off-by: Roman Pen <roman.penyaev@profitbricks.com>
Cc: Pedro Alves <palves@redhat.com>
Cc: Daniel Jacobowitz <drow@false.org>
Cc: Jan Kratochvil <jan.kratochvil@redhat.com>
Cc: gdb-patches@sourceware.org
QEMU guys who can be interested in this new gdb behaviour:
Cc: Stefan Hajnoczi <stefanha@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
---
gdb/corelow.c | 107 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 107 insertions(+)
diff --git a/gdb/corelow.c b/gdb/corelow.c
index c46af0a8a59d..8463717a23c9 100644
--- a/gdb/corelow.c
+++ b/gdb/corelow.c
@@ -74,6 +74,24 @@ static struct gdbarch *core_gdbarch = NULL;
unix child targets. */
static struct target_section_table *core_data;
+/* Cached registers. Once registers are modified (set) for a corefile,
+ they are cached and then are always fetched from get_core_registers().
+ This hairy hack is used only for one purpose: give a possibility to
+ investigate backtraces and debug jmp_buf (setjmp()) and user contexts
+ (makecontext()). */
+
+typedef char cachedreg_t[MAX_REGISTER_SIZE];
+
+struct cached_regs {
+ cachedreg_t *regs;
+ ptid_t ptid;
+ struct cached_regs *next;
+};
+
+/* Hash table of cached registers for each thread, where key is a ptid. */
+
+static struct cached_regs *core_cachedregs[128];
+
static void core_files_info (struct target_ops *);
static struct core_fns *sniff_core_bfd (bfd *);
@@ -183,12 +201,35 @@ gdb_check_format (bfd *abfd)
return (0);
}
+static inline unsigned
+ptid_to_hashtbl_index(ptid_t ptid)
+{
+ return ptid_get_lwp (ptid) % ARRAY_SIZE (core_cachedregs);
+}
+
+static inline struct cached_regs *
+find_cached_regs(ptid_t ptid)
+{
+ struct cached_regs *regs;
+
+ regs = core_cachedregs[ptid_to_hashtbl_index (ptid)];
+ for ( ; regs; regs = regs->next)
+ {
+ if (ptid_equal (regs->ptid, ptid))
+ break;
+ }
+
+ return regs;
+}
+
/* Discard all vestiges of any previous core file and mark data and
stack spaces as empty. */
static void
core_close (struct target_ops *self)
{
+ int i;
+
if (core_bfd)
{
int pid = ptid_get_pid (inferior_ptid);
@@ -213,6 +254,21 @@ core_close (struct target_ops *self)
}
core_vec = NULL;
core_gdbarch = NULL;
+
+ for (i = 0; i < ARRAY_SIZE (core_cachedregs); i++)
+ {
+ struct cached_regs *regs, *next;
+
+ regs = core_cachedregs[i];
+ while (regs)
+ {
+ next = regs->next;
+ xfree(regs->regs);
+ xfree(regs);
+ regs = next;
+ }
+ core_cachedregs[i] = NULL;
+ }
}
static void
@@ -610,6 +666,7 @@ get_core_registers (struct target_ops *ops,
{
int i;
struct gdbarch *gdbarch;
+ struct cached_regs *regs;
if (!(core_gdbarch && gdbarch_iterate_over_regset_sections_p (core_gdbarch))
&& (core_vec == NULL || core_vec->core_read_registers == NULL))
@@ -620,6 +677,19 @@ get_core_registers (struct target_ops *ops,
}
gdbarch = get_regcache_arch (regcache);
+ regs = find_cached_regs (inferior_ptid);
+
+ if (regs)
+ {
+ /* If registers were once modified (set) for a corefile,
+ follow this path and always return cached registers */
+
+ for (i = 0; i < gdbarch_num_regs (gdbarch); i++)
+ regcache_raw_supply(regcache, i, ®s->regs[i]);
+
+ return;
+ }
+
if (gdbarch_iterate_over_regset_sections_p (gdbarch))
gdbarch_iterate_over_regset_sections (gdbarch,
get_core_registers_cb,
@@ -639,6 +709,41 @@ get_core_registers (struct target_ops *ops,
}
static void
+set_core_registers (struct target_ops *self, struct regcache *regcache,
+ int regnum)
+{
+ struct cached_regs *regs;
+ struct gdbarch *gdbarch;
+ int i;
+
+ gdbarch = get_regcache_arch (regcache);
+ regs = find_cached_regs (inferior_ptid);
+
+ if (regs == NULL)
+ {
+ unsigned hind;
+
+ regs = (struct cached_regs *)xmalloc (sizeof(*regs));
+ regs->ptid = inferior_ptid;
+ regs->regs = (cachedreg_t *)xcalloc (gdbarch_num_regs (gdbarch),
+ sizeof(*regs->regs));
+ hind = ptid_to_hashtbl_index (inferior_ptid);
+ /* Add new cached registers to the head of the list */
+ regs->next = core_cachedregs[hind];
+ core_cachedregs[hind] = regs;
+ }
+
+ for (i = 0; i < gdbarch_num_regs (gdbarch); i++)
+ regcache_raw_collect (regcache, i, ®s->regs[i]);
+}
+
+static void
+prepare_core_registers (struct target_ops *self, struct regcache *arg1)
+{
+ /* nothing here */
+}
+
+static void
core_files_info (struct target_ops *t)
{
print_section_info (core_data, core_bfd);
@@ -1050,6 +1155,8 @@ init_core_ops (void)
core_ops.to_close = core_close;
core_ops.to_detach = core_detach;
core_ops.to_fetch_registers = get_core_registers;
+ core_ops.to_store_registers = set_core_registers;
+ core_ops.to_prepare_to_store = prepare_core_registers;
core_ops.to_xfer_partial = core_xfer_partial;
core_ops.to_files_info = core_files_info;
core_ops.to_insert_breakpoint = ignore;
--
2.11.0