+ *simm_ptr = (int) (((i & 0x8000) == 0x8000) ? 0xffff0000 | i : i);
+
+ return 1; /* Success */
+ }
+ else
+ {
+ return 0; /* Failure */
+ }
+}
+
+
+/* Analyse a l.sw instruction in form: l.sw I(rA),rB. This is used to
+ to parse store instructions during various prologue analysis routines. */
+
+static int
+or1k_analyse_l_sw (uint32_t inst,
+ int *simm_ptr, unsigned int *ra_ptr, unsigned int *rb_ptr)
+{
+ /* Instruction fields */
+ uint32_t ihi, ilo, ra, rb;
+
+ if (or1k_analyse_inst (inst, "11 0101 %5b %5b %5b %11b", &ihi, &ra, &rb,
+ &ilo))
+
+ {
+ /* Found it. Construct the result fields. */
+ *simm_ptr = (int) ((ihi << 11) | ilo);
+ *simm_ptr |= ((ihi & 0x10) == 0x10) ? 0xffff0000 : 0;
+
+ *ra_ptr = (unsigned int) ra;
+ *rb_ptr = (unsigned int) rb;
+
+ return 1; /* Success */
+ }
+ else
+ {
+ return 0; /* Failure */
+ }
+}
+
+
+/* Functions defining the architecture. */
+
+/* Implement the return_value gdbarch method. */
+
+static enum return_value_convention
+or1k_return_value (struct gdbarch *gdbarch, struct value *functype,
+ struct type *valtype, struct regcache *regcache,
+ gdb_byte *readbuf, const gdb_byte *writebuf)
+{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+ enum type_code rv_type = TYPE_CODE (valtype);
+ unsigned int rv_size = TYPE_LENGTH (valtype);
+ unsigned int bpw = (gdbarch_tdep (gdbarch))->bytes_per_word;
+
+ /* Deal with struct/union as addresses. If an array won't fit in a single
+ register it is returned as address. Anything larger than 2 registers needs
+ to also be passed as address (matches gcc default_return_in_memory). */
+ if ((TYPE_CODE_STRUCT == rv_type) || (TYPE_CODE_UNION == rv_type)
+ || ((TYPE_CODE_ARRAY == rv_type) && (rv_size > bpw))
+ || (rv_size > 2 * bpw))
+ {
+ if (readbuf != NULL)
+ {
+ ULONGEST tmp;
+
+ regcache_cooked_read_unsigned (regcache, OR1K_RV_REGNUM, &tmp);
+ read_memory (tmp, readbuf, rv_size);
+ }
+ if (writebuf != NULL)
+ {
+ ULONGEST tmp;
+
+ regcache_cooked_read_unsigned (regcache, OR1K_RV_REGNUM, &tmp);
+ write_memory (tmp, writebuf, rv_size);
+ }
+
+ return RETURN_VALUE_ABI_RETURNS_ADDRESS;
+ }
+
+ if (rv_size <= bpw)
+ {
+ /* Up to one word scalars are returned in R11. */
+ if (readbuf != NULL)
+ {
+ ULONGEST tmp;
+
+ regcache_cooked_read_unsigned (regcache, OR1K_RV_REGNUM, &tmp);
+ store_unsigned_integer (readbuf, rv_size, byte_order, tmp);
+
+ }
+ if (writebuf != NULL)
+ {
+ gdb_byte buf[4];
+ memset (buf, 0, sizeof (buf)); /* Zero pad if < bpw bytes */
+
+ if (BFD_ENDIAN_BIG == byte_order)
+ {
+ memcpy (buf + sizeof (buf) - rv_size, writebuf, rv_size);
+ }
+ else
+ {
+ memcpy (buf, writebuf, rv_size);
+ }
+
+ regcache_cooked_write (regcache, OR1K_RV_REGNUM, buf);
+ }
+ }
+ else
+ {
+ /* 2 word scalars are returned in r11/r12 (with the MS word in r11). */
+ if (readbuf != NULL)
+ {
+ ULONGEST tmp_lo;
+ ULONGEST tmp_hi;
+ ULONGEST tmp;
+
+ regcache_cooked_read_unsigned (regcache, OR1K_RV_REGNUM, &tmp_hi);
+ regcache_cooked_read_unsigned (regcache, OR1K_RV_REGNUM + 1,
+ &tmp_lo);
+ tmp = (tmp_hi << (bpw * 8)) | tmp_lo;
+
+ store_unsigned_integer (readbuf, rv_size, byte_order, tmp);
+ }
+ if (writebuf != NULL)
+ {
+ gdb_byte buf_lo[4];
+ gdb_byte buf_hi[4];
+
+ memset (buf_lo, 0, sizeof (buf_lo)); /* Zero pad if < bpw bytes */
+ memset (buf_hi, 0, sizeof (buf_hi)); /* Zero pad if < bpw bytes */
+
+ /* This is cheating. We assume that we fit in 2 words exactly, which
+ wouldn't work if we had (say) a 6-byte scalar type on a big
+ endian architecture (with the OpenRISC 1000 usually is). */
+ memcpy (buf_hi, writebuf, rv_size - bpw);
+ memcpy (buf_lo, writebuf + bpw, bpw);
+
+ regcache_cooked_write (regcache, OR1K_RV_REGNUM, buf_hi);
+ regcache_cooked_write (regcache, OR1K_RV_REGNUM + 1, buf_lo);
+ }
+ }
+
+ return RETURN_VALUE_REGISTER_CONVENTION;
+
+}
+
+/* OR1K always uses a l.trap instruction for breakpoints. */
+
+constexpr gdb_byte or1k_break_insn[] = {0x21, 0x00, 0x00, 0x01};
+
+typedef BP_MANIPULATION (or1k_break_insn) or1k_breakpoint;
+
+/* Implement the single_step_through_delay gdbarch method */
+
+static int
+or1k_single_step_through_delay (struct gdbarch *gdbarch,
+ struct frame_info *this_frame)
+{
+ ULONGEST val;
+ CORE_ADDR ppc;
+ CORE_ADDR npc;
+ CGEN_FIELDS tmp_fields;
+ const CGEN_INSN *insns;
+ struct regcache *regcache = get_current_regcache ();
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ /* Get and the previous and current instruction addresses. If they are not
+ adjacent, we cannot be in a delay slot. */
+ regcache_cooked_read_unsigned (regcache, OR1K_PPC_REGNUM, &val);
+ ppc = (CORE_ADDR) val;
+ regcache_cooked_read_unsigned (regcache, OR1K_NPC_REGNUM, &val);
+ npc = (CORE_ADDR) val;
+
+ if (0x4 != (npc - ppc))
+ {
+ return 0;
+ }
+
+ insns = cgen_lookup_insn (tdep->gdb_cgen_cpu_desc,
+ NULL,
+ or1k_fetch_instruction (gdbarch, ppc),
+ NULL, 32, &tmp_fields, 0);
+
+ /* TODO: we should add a delay slot flag to the CGEN_INSN and remove
+ * this hard coded test. */
+ return ((CGEN_INSN_NUM (insns) == OR1K_INSN_L_J)
+ || (CGEN_INSN_NUM (insns) == OR1K_INSN_L_JAL)
+ || (CGEN_INSN_NUM (insns) == OR1K_INSN_L_JR)
+ || (CGEN_INSN_NUM (insns) == OR1K_INSN_L_JALR)
+ || (CGEN_INSN_NUM (insns) == OR1K_INSN_L_BNF)
+ || (CGEN_INSN_NUM (insns) == OR1K_INSN_L_BF));
+
+}
+
+/* Name for or1k general registers. */
+
+static const char *const or1k_reg_names[OR1K_NUM_REGS] = {
+ /* general purpose registers */
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+ "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
+ "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
+
+ /* previous program counter, next program counter and status register */
+ "ppc", "npc", "sr"
+};
+
+/* Implement the register_name gdbarch method. */
+
+static const char *
+or1k_register_name (struct gdbarch *gdbarch, int regnum)
+{
+ if (0 <= regnum && regnum < OR1K_NUM_REGS)
+ {
+ return or1k_reg_names[regnum];
+ }
+ else
+ return NULL;
+}
+
+/* Implement the register_type gdbarch method. */
+
+static struct type *
+or1k_register_type (struct gdbarch *gdbarch, int regnum)
+{
+ if ((regnum >= 0) && (regnum < OR1K_NUM_REGS))
+ {
+ switch (regnum)
+ {
+ case OR1K_PPC_REGNUM:
+ case OR1K_NPC_REGNUM:
+ return builtin_type (gdbarch)->builtin_func_ptr; /* Pointer to code */
+
+ case OR1K_SP_REGNUM:
+ case OR1K_FP_REGNUM:
+ return builtin_type (gdbarch)->builtin_data_ptr; /* Pointer to data */
+
+ default:
+ return builtin_type (gdbarch)->builtin_uint32; /* Data */
+ }
+ }
+
+ internal_error (__FILE__, __LINE__,
+ _("or1k_register_type: illegal register number %d"),
+ regnum);
+
+}
+
+/* Implement the register_reggroup_p gdbarch method. */
+
+static int
+or1k_register_reggroup_p (struct gdbarch *gdbarch,
+ int regnum, struct reggroup *group)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ /* All register group */
+ if (group == all_reggroup)
+ {
+ return ((regnum >= 0)
+ && (regnum < OR1K_NUM_REGS)
+ && (or1k_register_name (gdbarch, regnum)[0] != '\0'));
+ }
+
+ /* For now everything except the PC */
+ if (group == general_reggroup)
+ {
+ return ((regnum >= OR1K_ZERO_REGNUM)
+ && (regnum < OR1K_MAX_GPR_REGS)
+ && (regnum != OR1K_PPC_REGNUM) && (regnum != OR1K_NPC_REGNUM));
+ }
+
+ if (group == float_reggroup)
+ {
+ return 0; /* No float regs. */
+ }
+
+ if (group == vector_reggroup)
+ {
+ return 0; /* No vector regs. */
+ }
+
+ /* For any that are not handled above. */
+ return default_register_reggroup_p (gdbarch, regnum, group);
+
+}
+
+
+static int
+or1k_is_arg_reg (unsigned int regnum)
+{
+ return (OR1K_FIRST_ARG_REGNUM <= regnum)
+ && (regnum <= OR1K_LAST_ARG_REGNUM);
+
+}
+
+
+static int
+or1k_is_callee_saved_reg (unsigned int regnum)
+{
+ return (OR1K_FIRST_SAVED_REGNUM <= regnum) && (0 == regnum % 2);
+
+}
+
+
+/* Implement the skip_prologue gdbarch method. */
+
+static CORE_ADDR
+or1k_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
+{
+ CORE_ADDR start_pc;
+ CORE_ADDR addr;
+ uint32_t inst;
+
+ unsigned int ra, rb, rd; /* for instruction analysis */
+ int simm;
+
+ int frame_size = 0;
+
+ /* Try using SAL first if we have symbolic information available. This only
+ works for DWARF 2, not STABS. */
+
+ if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
+ {
+ CORE_ADDR prologue_end = skip_prologue_using_sal (gdbarch, pc);
+
+ if (0 != prologue_end)
+ {
+ struct symtab_and_line prologue_sal = find_pc_line (start_pc, 0);
+ struct compunit_symtab *compunit
+ = SYMTAB_COMPUNIT (prologue_sal.symtab);
+ const char *debug_format = COMPUNIT_DEBUGFORMAT (compunit);
+
+ if ((NULL != debug_format)
+ && (strlen ("dwarf") <= strlen (debug_format))
+ && (0 == strncasecmp ("dwarf", debug_format, strlen ("dwarf"))))
+ {
+ return (prologue_end > pc) ? prologue_end : pc;
+ }
+ }
+ }
+
+ /* Look to see if we can find any of the standard prologue sequence. All
+ quite difficult, since any or all of it may be missing. So this is just a
+ best guess! */
+
+ addr = pc; /* Where we have got to */
+ inst = or1k_fetch_instruction (gdbarch, addr);
+
+ /* Look for the new stack pointer being set up. */
+ if (or1k_analyse_l_addi (inst, &rd, &ra, &simm)
+ && (OR1K_SP_REGNUM == rd) && (OR1K_SP_REGNUM == ra)
+ && (simm < 0) && (0 == (simm % 4)))
+ {
+ frame_size = -simm;
+ addr += OR1K_INSTLEN;
+ inst = or1k_fetch_instruction (gdbarch, addr);
+ }
+
+ /* Look for the frame pointer being manipulated. */
+ if (or1k_analyse_l_sw (inst, &simm, &ra, &rb)
+ && (OR1K_SP_REGNUM == ra) && (OR1K_FP_REGNUM == rb)
+ && (simm >= 0) && (0 == (simm % 4)))
+ {
+ addr += OR1K_INSTLEN;
+ inst = or1k_fetch_instruction (gdbarch, addr);
+
+ gdb_assert (or1k_analyse_l_addi (inst, &rd, &ra, &simm)
+ && (OR1K_FP_REGNUM == rd) && (OR1K_SP_REGNUM == ra)
+ && (simm == frame_size));
+
+ addr += OR1K_INSTLEN;
+ inst = or1k_fetch_instruction (gdbarch, addr);
+ }
+
+ /* Look for the link register being saved. */
+ if (or1k_analyse_l_sw (inst, &simm, &ra, &rb)
+ && (OR1K_SP_REGNUM == ra) && (OR1K_LR_REGNUM == rb)
+ && (simm >= 0) && (0 == (simm % 4)))
+ {
+ addr += OR1K_INSTLEN;
+ inst = or1k_fetch_instruction (gdbarch, addr);
+ }
+
+ /* Look for arguments or callee-saved register being saved. The register
+ must be one of the arguments (r3-r8) or the 10 callee saved registers
+ (r10, r12, r14, r16, r18, r20, r22, r24, r26, r28, r30). The base
+ register must be the FP (for the args) or the SP (for the callee_saved
+ registers). */
+ while (1)
+ {
+ if (or1k_analyse_l_sw (inst, &simm, &ra, &rb)
+ && (((OR1K_FP_REGNUM == ra) && or1k_is_arg_reg (rb))
+ || ((OR1K_SP_REGNUM == ra) && or1k_is_callee_saved_reg (rb)))
+ && (0 == (simm % 4)))
+ {
+ addr += OR1K_INSTLEN;
+ inst = or1k_fetch_instruction (gdbarch, addr);
+ }
+ else
+ {
+ /* Nothing else to look for. We have found the end of the prologue. */
+ return addr;
+ }
+ }
+}
+
+
+/* Implement the frame_align gdbarch method. */
+
+static CORE_ADDR
+or1k_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
+{
+ return align_down (sp, OR1K_STACK_ALIGN);
+
+}
+
+/* Implement the unwind_pc gdbarch method. */
+
+static CORE_ADDR
+or1k_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
+{
+ CORE_ADDR pc;
+
+ if (frame_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog, "or1k_unwind_pc, next_frame=%d\n",
+ frame_relative_level (next_frame));
+ }
+
+ pc = frame_unwind_register_unsigned (next_frame, OR1K_NPC_REGNUM);
+
+ if (frame_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog, "or1k_unwind_pc, pc=0x%p\n",
+ (void *) pc);
+ }
+
+ return pc;
+
+}
+
+/* Implement the unwind_sp gdbarch method. */
+
+static CORE_ADDR
+or1k_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
+{
+ CORE_ADDR sp;
+
+ if (frame_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog, "or1k_unwind_sp, next_frame=%d\n",
+ frame_relative_level (next_frame));
+ }
+
+ sp = frame_unwind_register_unsigned (next_frame, OR1K_SP_REGNUM);
+
+ if (frame_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog, "or1k_unwind_sp, sp=0x%p\n",
+ (void *) sp);
+ }
+
+ return sp;
+
+}
+
+/* Implement the push_dummy_code gdbarch method. */
+
+static CORE_ADDR
+or1k_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
+ CORE_ADDR function, struct value **args, int nargs,
+ struct type *value_type, CORE_ADDR * real_pc,
+ CORE_ADDR * bp_addr, struct regcache *regcache)
+{
+ CORE_ADDR bp_slot;
+
+ /* Reserve enough room on the stack for our breakpoint instruction. */
+ bp_slot = sp - 4;
+ /* Store the address of that breakpoint. */
+ *bp_addr = bp_slot;
+ /* keeping the stack aligned. */
+ sp = or1k_frame_align (gdbarch, bp_slot);
+ /* The call starts at the callee's entry point. */
+ *real_pc = function;
+
+ return sp;
+
+}
+
+/* Implement the push_dummy_call gdbarch method. */
+
+static CORE_ADDR
+or1k_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
+ struct regcache *regcache, CORE_ADDR bp_addr,
+ int nargs, struct value **args, CORE_ADDR sp,
+ int struct_return, CORE_ADDR struct_addr)
+{
+
+ int argreg;
+ int argnum;
+ int first_stack_arg;
+ int stack_offset = 0;
+ int heap_offset = 0;
+ CORE_ADDR heap_sp = sp - 128;
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+ unsigned int bpa = (gdbarch_tdep (gdbarch))->bytes_per_address;
+ unsigned int bpw = (gdbarch_tdep (gdbarch))->bytes_per_word;
+ struct type *func_type = value_type (function);
+
+ /* Return address */
+ regcache_cooked_write_unsigned (regcache, OR1K_LR_REGNUM, bp_addr);
+
+ /* Register for the next argument. */
+ argreg = OR1K_FIRST_ARG_REGNUM;
+
+ /* Location for a returned structure. This is passed as a silent first
+ argument. */
+ if (struct_return)
+ {
+ regcache_cooked_write_unsigned (regcache, OR1K_FIRST_ARG_REGNUM,
+ struct_addr);
+ argreg++;
+ }
+
+ /* Put as many args as possible in registers */
+ for (argnum = 0; argnum < nargs; argnum++)
+ {
+ const gdb_byte *val;
+ gdb_byte valbuf[sizeof (ULONGEST)];
+
+ struct value *arg = args[argnum];
+ struct type *arg_type = check_typedef (value_type (arg));
+ int len = arg_type->length;
+ enum type_code typecode = arg_type->main_type->code;
+
+ if (TYPE_VARARGS (func_type) && argnum >= TYPE_NFIELDS (func_type))
+ {
+ break; /* end or regular args, varargs go to stack */
+ }
+
+ /* Extract the value, either a reference or the data */
+ if ((TYPE_CODE_STRUCT == typecode) || (TYPE_CODE_UNION == typecode)
+ || (len > bpw * 2))
+ {
+ CORE_ADDR valaddr = value_address (arg);
+
+ /* if the arg is fabricated (i.e. 3*i, instead of i) valaddr is undefined */
+ if (valaddr == 0)
+ {
+ /* The argument needs to be copied into the target space. Since
+ the bottom of the stack is reserved for function arguments
+ we store this at the these at the top growing down. */
+ heap_offset += align_up (len, bpw);
+ valaddr = heap_sp + heap_offset;
+
+ write_memory (valaddr, value_contents (arg), len);
+ }
+
+ /* The ABI passes all structures by reference, so get its address. */
+ store_unsigned_integer (valbuf, bpa, byte_order, valaddr);
+ len = bpa;
+ val = valbuf;
+ }
+ else
+ {
+ /* Everything else, we just get the value. */
+ val = value_contents (arg);
+ }
+
+ /* Stick the value in a register */
+ if (len > bpw)
+ {
+ /* Big scalars use two registers, but need NOT be pair aligned. */
+
+ if (argreg <= (OR1K_LAST_ARG_REGNUM - 1))
+ {
+ ULONGEST regval = extract_unsigned_integer (val, len, byte_order);
+
+ unsigned int bits_per_word = bpw * 8;
+ ULONGEST mask = (((ULONGEST) 1) << bits_per_word) - 1;
+ ULONGEST lo = regval & mask;
+ ULONGEST hi = regval >> bits_per_word;
+
+ regcache_cooked_write_unsigned (regcache, argreg, hi);
+ regcache_cooked_write_unsigned (regcache, argreg + 1, lo);
+ argreg += 2;
+ }
+ else
+ {
+ /* Run out of regs */
+ break;
+ }
+ }
+ else if (argreg <= OR1K_LAST_ARG_REGNUM)
+ {
+ /* Smaller scalars fit in a single register */
+ regcache_cooked_write_unsigned (regcache, argreg,
+ extract_unsigned_integer (val, len,
+ byte_order));
+ argreg++;
+ }
+ else
+ {
+ /* Run out of regs */
+ break;
+ }
+ }
+
+ first_stack_arg = argnum;
+
+ /* If we get here with argnum < nargs, then arguments remain to be placed on
+ the stack. This is tricky, since they must be pushed in reverse order and
+ the stack in the end must be aligned. The only solution is to do it in
+ two stages, the first to compute the stack size, the second to save the
+ args. */
+
+ for (argnum = first_stack_arg; argnum < nargs; argnum++)
+ {
+ struct value *arg = args[argnum];
+ struct type *arg_type = check_typedef (value_type (arg));
+ int len = arg_type->length;
+ enum type_code typecode = arg_type->main_type->code;
+
+ if ((TYPE_CODE_STRUCT == typecode) || (TYPE_CODE_UNION == typecode)
+ || (len > bpw * 2))
+ {
+ /* Structures are passed as addresses */
+ sp -= bpa;
+ }
+ else
+ {
+ /* Big scalars use more than one word. Code here allows for future
+ quad-word entities (e.g. long double) */
+ sp -= align_up (len, bpw);
+ }
+
+ /* ensure our dummy heap doesn't touch the stack, this could only happen
+ if we have many arguments including fabricated arguments */
+ gdb_assert (heap_offset == 0 || ((heap_sp + heap_offset) < sp));
+ }
+
+ sp = gdbarch_frame_align (gdbarch, sp);
+ stack_offset = 0;
+
+ /* Push the remaining args on the stack */
+ for (argnum = first_stack_arg; argnum < nargs; argnum++)
+ {
+ const gdb_byte *val;
+ gdb_byte valbuf[sizeof (ULONGEST)];
+
+ struct value *arg = args[argnum];
+ struct type *arg_type = check_typedef (value_type (arg));
+ int len = arg_type->length;
+ enum type_code typecode = arg_type->main_type->code;
+ /* The EABI passes structures that do not fit in a register by
+ reference. In all other cases, pass the structure by value. */
+ if ((TYPE_CODE_STRUCT == typecode) || (TYPE_CODE_UNION == typecode)
+ || (len > bpw * 2))
+ {
+ store_unsigned_integer (valbuf, bpa, byte_order,
+ value_address (arg));
+ len = bpa;
+ val = valbuf;
+ }
+ else
+ {
+ val = value_contents (arg);
+ }
+
+ while (len > 0)
+ {
+ int partial_len = (len < bpw ? len : bpw);
+
+ write_memory (sp + stack_offset, val, partial_len);
+ stack_offset += align_up (partial_len, bpw);
+ len -= partial_len;
+ val += partial_len;
+ }
+ }
+
+ /* Save the updated stack pointer */
+ regcache_cooked_write_unsigned (regcache, OR1K_SP_REGNUM, sp);
+
+ if (heap_offset > 0)
+ {
+ sp = heap_sp;
+ }
+
+ return sp;
+
+}
+
+
+/* Implement the dummy_id gdbarch method. */
+
+static struct frame_id
+or1k_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
+{
+ return frame_id_build (get_frame_sp (this_frame),
+ get_frame_pc (this_frame));
+
+}
+
+
+
+
+/* Support functions for frame handling */
+
+/* Initialize a prologue cache
+
+ We build a cache, saying where registers of the PREV frame can be found
+ from the data so far set up in this THIS.
+
+ We also compute a unique ID for this frame, based on the function start
+ address and the stack pointer (as it will be, even if it has yet to be
+ computed.
+
+ STACK FORMAT
+ ============
+
+ The OR1K has a falling stack frame and a simple prolog. The Stack pointer
+ is R1 and the frame pointer R2. The frame base is therefore the address
+ held in R2 and the stack pointer (R1) is the frame base of the NEXT frame.
+
+ l.addi r1,r1,-frame_size # SP now points to end of new stack frame
+
+ The stack pointer may not be set up in a frameless function (e.g. a simple
+ leaf function).
+
+ l.sw fp_loc(r1),r2 # old FP saved in new stack frame
+ l.addi r2,r1,frame_size # FP now points to base of new stack frame
+
+ The frame pointer is not necessarily saved right at the end of the stack
+ frame - OR1K saves enough space for any args to called functions right at
+ the end (this is a difference from the Architecture Manual).
+
+ l.sw lr_loc(r1),r9 # Link (return) address
+
+ The link register is usally saved at fp_loc - 4. It may not be saved at all
+ in a leaf function.
+
+ l.sw reg_loc(r1),ry # Save any callee saved regs
+
+ The offsets x for the callee saved registers generally (always?) rise in
+ increments of 4, starting at fp_loc + 4. If the frame pointer is omitted
+ (an option to GCC), then it may not be saved at all. There may be no callee
+ saved registers.
+
+ So in summary none of this may be present. However what is present seems
+ always to follow this fixed order, and occur before any substantive code
+ (it is possible for GCC to have more flexible scheduling of the prologue,
+ but this does not seem to occur for OR1K).
+
+ ANALYSIS
+ ========
+
+ This prolog is used, even for -O3 with GCC.
+
+ All this analysis must allow for the possibility that the PC is in the
+ middle of the prologue. Data in the cache should only be set up insofar as
+ it has been computed.
+
+ HOWEVER. The frame_id must be created with the SP *as it will be* at the
+ end of the Prologue. Otherwise a recursive call, checking the frame with
+ the PC at the start address will end up with the same frame_id as the
+ caller.
+
+ A suite of "helper" routines are used, allowing reuse for
+ or1k_skip_prologue().
+
+ Reportedly, this is only valid for frames less than 0x7fff in size. */
+
+static struct trad_frame_cache *
+or1k_frame_cache (struct frame_info *this_frame, void **prologue_cache)
+{
+ struct gdbarch *gdbarch;
+ struct trad_frame_cache *info;
+
+ CORE_ADDR this_pc;
+ CORE_ADDR this_sp;
+ CORE_ADDR this_sp_for_id;
+ int frame_size = 0;
+
+ CORE_ADDR start_addr;
+ CORE_ADDR end_addr;
+
+ if (frame_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog,
+ "or1k_frame_cache, prologue_cache = 0x%p\n",
+ *prologue_cache);
+ }
+
+ /* Nothing to do if we already have this info. */
+ if (NULL != *prologue_cache)
+ {
+ return (struct trad_frame_cache *) *prologue_cache;
+ }
+
+ /* Get a new prologue cache and populate it with default values. */
+ info = trad_frame_cache_zalloc (this_frame);
+ *prologue_cache = info;
+
+ /* Find the start address of THIS function (which is a NORMAL frame, even if
+ the NEXT frame is the sentinel frame) and the end of its prologue. */
+ this_pc = get_frame_pc (this_frame);
+ find_pc_partial_function (this_pc, NULL, &start_addr, NULL);
+
+ /* Get the stack pointer if we have one (if there's no process executing yet
+ we won't have a frame. */
+ this_sp = (NULL == this_frame) ? 0 :
+ get_frame_register_unsigned (this_frame, OR1K_SP_REGNUM);
+
+ /* Return early if GDB couldn't find the function. */
+ if (start_addr == 0)
+ {
+ if (frame_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog, " couldn't find function\n");
+ }
+
+ /* JPB: 28-Apr-11. This is a temporary patch, to get round GDB crashing
+ right at the beginning. Build the frame ID as best we can. */
+ trad_frame_set_id (info, frame_id_build (this_sp, this_pc));
+
+ return info;
+ }
+
+
+ /* The default frame base of THIS frame (for ID purposes only - frame base
+ is an overloaded term) is its stack pointer. For now we use the value of
+ the SP register in THIS frame. However if the PC is in the prologue of
+ THIS frame, before the SP has been set up, then the value will actually
+ be that of the PREV frame, and we'll need to adjust it later. */
+ trad_frame_set_this_base (info, this_sp);
+ this_sp_for_id = this_sp;
+
+ /* The default is to find the PC of the PREVIOUS frame in the link register
+ of this frame. This may be changed if we find the link register was saved
+ on the stack. */
+ trad_frame_set_reg_realreg (info, OR1K_NPC_REGNUM, OR1K_LR_REGNUM);
+
+ /* We should only examine code that is in the prologue. This is all code up
+ to (but not including) end_addr. We should only populate the cache while
+ the address is up to (but not including) the PC or end_addr, whichever is
+ first. */
+ gdbarch = get_frame_arch (this_frame);
+ end_addr = or1k_skip_prologue (gdbarch, start_addr);
+
+ /* All the following analysis only occurs if we are in the prologue and have
+ executed the code. Check we have a sane prologue size, and if zero we
+ are frameless and can give up here. */
+ if (end_addr < start_addr)
+ {
+ throw_quit ("end addr 0x%08x is less than start addr 0x%08x\n",
+ (unsigned int) end_addr, (unsigned int) start_addr);
+ }
+
+ if (end_addr == start_addr)
+ {
+ frame_size = 0;
+ }
+ else
+ {
+ /* have a frame. Look for the various components */
+ CORE_ADDR addr = start_addr; /* Where we have got to */
+ uint32_t inst = or1k_fetch_instruction (gdbarch, addr);
+
+ unsigned int ra, rb, rd; /* For instruction analysis */
+ int simm;
+
+ /* Look for the new stack pointer being set up. */
+ if (or1k_analyse_l_addi (inst, &rd, &ra, &simm)
+ && (OR1K_SP_REGNUM == rd) && (OR1K_SP_REGNUM == ra)
+ && (simm < 0) && (0 == (simm % 4)))
+ {
+ frame_size = -simm;
+ addr += OR1K_INSTLEN;
+ inst = or1k_fetch_instruction (gdbarch, addr);
+
+ /* If the PC has not actually got to this point, then the frame base
+ will be wrong, and we adjust it.
+
+ If we are past this point, then we need to populate the stack
+ accoringly. */
+ if (this_pc <= addr)
+ {
+ /* Only do if executing */
+ if (0 != this_sp)
+ {
+ this_sp_for_id = this_sp + frame_size;
+ trad_frame_set_this_base (info, this_sp_for_id);
+ }
+ }
+ else
+ {
+ /* We are past this point, so the stack pointer of the PREV
+ frame is frame_size greater than the stack pointer of THIS
+ frame. */
+ trad_frame_set_reg_value (info, OR1K_SP_REGNUM,
+ this_sp + frame_size);
+ }
+ }
+
+ /* From now on we are only populating the cache, so we stop once we get
+ to either the end OR the current PC. */
+ end_addr = (this_pc < end_addr) ? this_pc : end_addr;
+
+ /* Look for the frame pointer being manipulated. */
+ if ((addr < end_addr)
+ && or1k_analyse_l_sw (inst, &simm, &ra, &rb)
+ && (OR1K_SP_REGNUM == ra) && (OR1K_FP_REGNUM == rb)
+ && (simm >= 0) && (0 == (simm % 4)))
+ {
+ addr += OR1K_INSTLEN;
+ inst = or1k_fetch_instruction (gdbarch, addr);
+
+ /* At this stage, we can find the frame pointer of the PREVIOUS
+ frame on the stack of the current frame. */
+ trad_frame_set_reg_addr (info, OR1K_FP_REGNUM, this_sp + simm);
+
+ /* Look for the new frame pointer being set up */
+ if (addr < end_addr)
+ {
+ gdb_assert (or1k_analyse_l_addi (inst, &rd, &ra, &simm)
+ && (OR1K_FP_REGNUM == rd) && (OR1K_SP_REGNUM == ra)
+ && (simm == frame_size));
+
+ addr += OR1K_INSTLEN;
+ inst = or1k_fetch_instruction (gdbarch, addr);
+
+ /* If we have got this far, the stack pointer of the PREVIOUS
+ frame is the frame pointer of THIS frame. */
+ trad_frame_set_reg_realreg (info, OR1K_SP_REGNUM,
+ OR1K_FP_REGNUM);
+ }
+ }
+
+ /* Look for the link register being saved */
+ if ((addr < end_addr)
+ && or1k_analyse_l_sw (inst, &simm, &ra, &rb)
+ && (OR1K_SP_REGNUM == ra) && (OR1K_LR_REGNUM == rb)
+ && (simm >= 0) && (0 == (simm % 4)))
+ {
+ addr += OR1K_INSTLEN;
+ inst = or1k_fetch_instruction (gdbarch, addr);
+
+ /* If the link register is saved in the THIS frame, it holds the
+ value of the PC in the PREVIOUS frame. This overwrites the
+ previous information about finding the PC in the link
+ register. */
+ trad_frame_set_reg_addr (info, OR1K_NPC_REGNUM, this_sp + simm);
+ }
+
+ /* Look for arguments or callee-saved register being saved. The register
+ must be one of the arguments (r3-r8) or the 10 callee saved registers
+ (r10, r12, r14, r16, r18, r20, r22, r24, r26, r28, r30). The base
+ register must be the FP (for the args) or the SP (for the
+ callee_saved registers). */
+ while (addr < end_addr)
+ {
+ if (or1k_analyse_l_sw (inst, &simm, &ra, &rb)
+ && (((OR1K_FP_REGNUM == ra) && or1k_is_arg_reg (rb))
+ || ((OR1K_SP_REGNUM == ra)
+ && or1k_is_callee_saved_reg (rb))) && (0 == (simm % 4)))
+ {
+ addr += OR1K_INSTLEN;
+ inst = or1k_fetch_instruction (gdbarch, addr);
+
+ /* The register in the PREVIOUS frame can be found at this
+ location in THIS frame */
+ trad_frame_set_reg_addr (info, rb, this_sp + simm);
+ }
+ else
+ {
+ break; /* Not a register save instruction */
+ }
+ }
+ }
+
+ /* Build the frame ID */
+ trad_frame_set_id (info, frame_id_build (this_sp_for_id, start_addr));
+
+ if (frame_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog, " this_sp_for_id = 0x%p\n",
+ (void *) this_sp_for_id);
+ fprintf_unfiltered (gdb_stdlog, " start_addr = 0x%p\n",
+ (void *) start_addr);
+ }
+
+ return info;
+
+}
+
+
+/* Implement the this_id function for the stub unwinder. */
+
+static void
+or1k_frame_this_id (struct frame_info *this_frame,
+ void **prologue_cache, struct frame_id *this_id)
+{
+ struct trad_frame_cache *info = or1k_frame_cache (this_frame,
+ prologue_cache);
+
+ trad_frame_get_id (info, this_id);
+
+}
+
+
+/* Implement the prev_register function for the stub unwinder. */
+
+static struct value *
+or1k_frame_prev_register (struct frame_info *this_frame,
+ void **prologue_cache, int regnum)
+{
+ struct trad_frame_cache *info = or1k_frame_cache (this_frame,
+ prologue_cache);
+
+ return trad_frame_get_register (info, this_frame, regnum);
+
+}
+
+/* Data structures for the normal prologue-analysis-based
+ unwinder. */
+
+static const struct frame_unwind or1k_frame_unwind = {
+ .type = NORMAL_FRAME,
+ .stop_reason = default_frame_unwind_stop_reason,
+ .this_id = or1k_frame_this_id,
+ .prev_register = or1k_frame_prev_register,
+ .unwind_data = NULL,
+ .sniffer = default_frame_sniffer,
+ .dealloc_cache = NULL,
+ .prev_arch = NULL
+};
+
+/* Architecture initialization for OpenRISC 1000. */
+
+static struct gdbarch *
+or1k_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+{
+ static struct frame_base or1k_frame_base;
+ struct gdbarch *gdbarch;
+ struct gdbarch_tdep *tdep;
+ const struct bfd_arch_info *binfo;
+ struct tdesc_arch_data *tdesc_data = NULL;
+
+ int i;
+ int reg_index = 0;
+ int retval;
+ int group;
+
+ /* Find a candidate among the list of pre-declared architectures. */
+ arches = gdbarch_list_lookup_by_info (arches, &info);
+ if (NULL != arches)
+ {
+ return arches->gdbarch;
+ }
+
+ /* None found, create a new architecture from the information
+ provided. Can't initialize all the target dependencies until we actually
+ know which target we are talking to, but put in some defaults for now. */
+
+ binfo = info.bfd_arch_info;
+ tdep = XNEW (struct gdbarch_tdep);