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[PATCH 05/17] Fix spelling in comments in C source files (opcodes)
- From: Ambrogino Modigliani <ambrogino dot modigliani at gmail dot com>
- To: gdb-patches at sourceware dot org, pedro_alves at portugalmail dot pt, ambrogino dot modigliani at gmail dot com, ambrogino dot modigliani at mail dot com
- Date: Fri, 25 Nov 2016 20:46:31 +0100
- Subject: [PATCH 05/17] Fix spelling in comments in C source files (opcodes)
- Authentication-results: sourceware.org; auth=none
- References: <1480103203-9710-1-git-send-email-ambrogino.modigliani@mail.com>
opcodes/ChangeLog:
* aarch64-asm.c: Fix spelling in comments.
* aarch64-dis.c: Fix spelling in comments.
* arc-dis.c: Fix spelling in comments.
* arm-dis.c: Fix spelling in comments.
* cgen-asm.c: Fix spelling in comments.
* cgen-dis.c: Fix spelling in comments.
* cgen-opc.c: Fix spelling in comments.
* dis-buf.c: Fix spelling in comments.
* epiphany-asm.c: Fix spelling in comments.
* epiphany-dis.c: Fix spelling in comments.
* fr30-asm.c: Fix spelling in comments.
* fr30-dis.c: Fix spelling in comments.
* frv-asm.c: Fix spelling in comments.
* frv-dis.c: Fix spelling in comments.
* frv-opc.c: Fix spelling in comments.
* hppa-dis.c: Fix spelling in comments.
* i386-dis.c: Fix spelling in comments.
* i386-opc.h: Fix spelling in comments.
* ip2k-asm.c: Fix spelling in comments.
* ip2k-dis.c: Fix spelling in comments.
* iq2000-asm.c: Fix spelling in comments.
* iq2000-dis.c: Fix spelling in comments.
* lm32-asm.c: Fix spelling in comments.
* lm32-dis.c: Fix spelling in comments.
* m32c-asm.c: Fix spelling in comments.
* m32c-dis.c: Fix spelling in comments.
* m32r-asm.c: Fix spelling in comments.
* m32r-dis.c: Fix spelling in comments.
* m68hc11-opc.c: Fix spelling in comments.
* m68k-dis.c: Fix spelling in comments.
* m68k-opc.c: Fix spelling in comments.
* mep-asm.c: Fix spelling in comments.
* mep-dis.c: Fix spelling in comments.
* metag-dis.c: Fix spelling in comments.
* msp430-decode.c: Fix spelling in comments.
* msp430-dis.c: Fix spelling in comments.
* mt-asm.c: Fix spelling in comments.
* mt-dis.c: Fix spelling in comments.
* ns32k-dis.c: Fix spelling in comments.
* opintl.h: Fix spelling in comments.
* or1k-asm.c: Fix spelling in comments.
* or1k-desc.h: Fix spelling in comments.
* or1k-dis.c: Fix spelling in comments.
* ppc-opc.c: Fix spelling in comments.
* sh-dis.c: Fix spelling in comments.
* sh64-dis.c: Fix spelling in comments.
* tic30-dis.c: Fix spelling in comments.
* v850-opc.c: Fix spelling in comments.
* xc16x-asm.c: Fix spelling in comments.
* xc16x-dis.c: Fix spelling in comments.
* xstormy16-asm.c: Fix spelling in comments.
* xstormy16-dis.c: Fix spelling in comments.
* xtensa-dis.c: Fix spelling in comments.
---
opcodes/aarch64-asm.c | 2 +-
opcodes/aarch64-dis.c | 4 ++--
opcodes/arc-dis.c | 6 +++---
opcodes/arm-dis.c | 8 ++++----
opcodes/cgen-asm.c | 4 ++--
opcodes/cgen-dis.c | 4 ++--
opcodes/cgen-opc.c | 2 +-
opcodes/dis-buf.c | 2 +-
opcodes/epiphany-asm.c | 2 +-
opcodes/epiphany-dis.c | 2 +-
opcodes/fr30-asm.c | 2 +-
opcodes/fr30-dis.c | 2 +-
opcodes/frv-asm.c | 2 +-
opcodes/frv-dis.c | 2 +-
opcodes/frv-opc.c | 2 +-
opcodes/hppa-dis.c | 2 +-
opcodes/i386-dis.c | 2 +-
opcodes/i386-opc.h | 2 +-
opcodes/ip2k-asm.c | 2 +-
opcodes/ip2k-dis.c | 2 +-
opcodes/iq2000-asm.c | 2 +-
opcodes/iq2000-dis.c | 2 +-
opcodes/lm32-asm.c | 2 +-
opcodes/lm32-dis.c | 2 +-
opcodes/m32c-asm.c | 2 +-
opcodes/m32c-dis.c | 2 +-
opcodes/m32r-asm.c | 2 +-
opcodes/m32r-dis.c | 2 +-
opcodes/m68hc11-opc.c | 2 +-
opcodes/m68k-dis.c | 2 +-
opcodes/m68k-opc.c | 2 +-
opcodes/mep-asm.c | 2 +-
opcodes/mep-dis.c | 6 +++---
opcodes/metag-dis.c | 2 +-
opcodes/msp430-decode.c | 2 +-
opcodes/msp430-dis.c | 2 +-
opcodes/mt-asm.c | 2 +-
opcodes/mt-dis.c | 2 +-
opcodes/ns32k-dis.c | 2 +-
opcodes/opintl.h | 2 +-
opcodes/or1k-asm.c | 2 +-
opcodes/or1k-desc.h | 2 +-
opcodes/or1k-dis.c | 2 +-
opcodes/ppc-opc.c | 6 +++---
opcodes/sh-dis.c | 2 +-
opcodes/sh64-dis.c | 2 +-
opcodes/tic30-dis.c | 2 +-
opcodes/v850-opc.c | 2 +-
opcodes/xc16x-asm.c | 2 +-
opcodes/xc16x-dis.c | 2 +-
opcodes/xstormy16-asm.c | 2 +-
opcodes/xstormy16-dis.c | 2 +-
opcodes/xtensa-dis.c | 2 +-
53 files changed, 65 insertions(+), 65 deletions(-)
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index cfe6630..9f31e35 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -29,7 +29,7 @@
these fields where the VALUE will be inserted into CODE. MASK can be zero or
the base mask of the opcode.
- N.B. the fields are required to be in such an order than the least signficant
+ N.B. the fields are required to be in such an order than the least significant
field for VALUE comes the first, e.g. the <index> in
SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
is encoded in H:L:M in some cases, the fields H:L:M should be passed in
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index bcf5232..e445cf7 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -117,7 +117,7 @@ parse_aarch64_dis_options (const char *options)
these fields where the VALUE will be extracted from CODE and returned.
MASK can be zero or the base mask of the opcode.
- N.B. the fields are required to be in such an order than the most signficant
+ N.B. the fields are required to be in such an order than the most significant
field for VALUE comes the first, e.g. the <index> in
SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
is encoded in H:L:M in some cases, the fields H:L:M should be passed in
@@ -3125,7 +3125,7 @@ print_insn_aarch64 (bfd_vma pc,
n = last_mapping_sym;
/* No mapping symbol found at this address. Look backwards
- for a preceeding one. */
+ for a preceding one. */
for (; n >= 0; n--)
{
if (get_sym_code_type (info, n, &type))
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index 31b5a91..9abc65b 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -77,7 +77,7 @@ static int addrtypenames_max = ARC_NUM_ADDRTYPES - 1;
static const char * const addrtypeunknown = "unknown";
/* This structure keeps track which instruction class(es)
- should be ignored durring disassembling. */
+ should be ignored during disassembling. */
typedef struct skipclass
{
@@ -86,7 +86,7 @@ typedef struct skipclass
struct skipclass *nxt;
} skipclass_t, *linkclass;
-/* Intial classes of instructions to be consider first when
+/* Initial classes of instructions to be consider first when
disassembling. */
static linkclass decodelist = NULL;
@@ -399,7 +399,7 @@ find_format (bfd_vma memaddr,
if (opcode == NULL)
{
(*info->fprintf_func) (info->stream, "\
-An error occured while generating the extension instruction operations");
+An error occurred while generating the extension instruction operations");
*opcode_result = NULL;
return FALSE;
}
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 87d4930..79fad83 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -3342,7 +3342,7 @@ arm_decode_shift (long given, fprintf_ftype func, void *stream,
#define PRE_BIT_SET (given & (1 << P_BIT))
/* Print one coprocessor instruction on INFO->STREAM.
- Return TRUE if the instuction matched, FALSE if this is not a
+ Return TRUE if the instruction matched, FALSE if this is not a
recognised coprocessor instruction. */
static bfd_boolean
@@ -4083,7 +4083,7 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
}
/* Print one neon instruction on INFO->STREAM.
- Return TRUE if the instuction matched, FALSE if this is not a
+ Return TRUE if the instruction matched, FALSE if this is not a
recognised neon instruction. */
static bfd_boolean
@@ -6141,10 +6141,10 @@ parse_disassembler_options (char *options)
{
parse_arm_disassembler_option (options);
- /* Skip forward to next seperator. */
+ /* Skip forward to next separator. */
while ((*options) && (! ISSPACE (*options)) && (*options != ','))
++ options;
- /* Skip forward past seperators. */
+ /* Skip forward past separators. */
while (ISSPACE (*options) || (*options == ','))
++ options;
}
diff --git a/opcodes/cgen-asm.c b/opcodes/cgen-asm.c
index 73ac378..da58559 100644
--- a/opcodes/cgen-asm.c
+++ b/opcodes/cgen-asm.c
@@ -60,7 +60,7 @@ cgen_init_parse_operand (CGEN_CPU_DESC cd)
The result is a pointer to the next entry to use.
The table is scanned backwards as additions are made to the front of the
- list and we want earlier ones to be prefered. */
+ list and we want earlier ones to be preferred. */
static CGEN_INSN_LIST *
hash_insn_array (CGEN_CPU_DESC cd,
@@ -156,7 +156,7 @@ build_asm_hash_table (CGEN_CPU_DESC cd)
asm_hash_table, hash_entry_buf);
/* Add runtime added insns.
- Later added insns will be prefered over earlier ones. */
+ Later added insns will be preferred over earlier ones. */
hash_entry_buf = hash_insn_list (cd, insn_table->new_entries,
asm_hash_table, hash_entry_buf);
diff --git a/opcodes/cgen-dis.c b/opcodes/cgen-dis.c
index 2d0f701..d89c492 100644
--- a/opcodes/cgen-dis.c
+++ b/opcodes/cgen-dis.c
@@ -94,7 +94,7 @@ add_insn_to_hash_chain (CGEN_INSN_LIST *hentbuf,
The result is a pointer to the next entry to use.
The table is scanned backwards as additions are made to the front of the
- list and we want earlier ones to be prefered. */
+ list and we want earlier ones to be preferred. */
static CGEN_INSN_LIST *
hash_insn_array (CGEN_CPU_DESC cd,
@@ -210,7 +210,7 @@ build_dis_hash_table (CGEN_CPU_DESC cd)
dis_hash_table, hash_entry_buf);
/* Add runtime added insns.
- Later added insns will be prefered over earlier ones. */
+ Later added insns will be preferred over earlier ones. */
hash_entry_buf = hash_insn_list (cd, insn_table->new_entries,
dis_hash_table, hash_entry_buf);
diff --git a/opcodes/cgen-opc.c b/opcodes/cgen-opc.c
index 543ce32..e8711d9 100644
--- a/opcodes/cgen-opc.c
+++ b/opcodes/cgen-opc.c
@@ -249,7 +249,7 @@ build_keyword_hash_tables (CGEN_KEYWORD *kt)
memset (kt->value_hash_table, 0, size * sizeof (CGEN_KEYWORD_ENTRY *));
/* The table is scanned backwards as we want keywords appearing earlier to
- be prefered over later ones. */
+ be preferred over later ones. */
for (i = kt->num_init_entries - 1; i >= 0; --i)
cgen_keyword_add (kt, &kt->init_entries[i]);
}
diff --git a/opcodes/dis-buf.c b/opcodes/dis-buf.c
index d46c772..76722a8 100644
--- a/opcodes/dis-buf.c
+++ b/opcodes/dis-buf.c
@@ -71,7 +71,7 @@ perror_memory (int status,
}
}
-/* This could be in a separate file, to save miniscule amounts of space
+/* This could be in a separate file, to save minuscule amounts of space
in statically linked executables. */
/* Just print the address is hex. This is included for completeness even
diff --git a/opcodes/epiphany-asm.c b/opcodes/epiphany-asm.c
index 41acc42..9ed5f6e 100644
--- a/opcodes/epiphany-asm.c
+++ b/opcodes/epiphany-asm.c
@@ -742,7 +742,7 @@ parse_insn_normal (CGEN_CPU_DESC cd,
still needs to be converted to target byte order, otherwise BUF is an array
of bytes in target byte order.
The result is a pointer to the insn's entry in the opcode table,
- or NULL if an error occured (an error message will have already been
+ or NULL if an error occurred (an error message will have already been
printed).
Note that when processing (non-alias) macro-insns,
diff --git a/opcodes/epiphany-dis.c b/opcodes/epiphany-dis.c
index 2838b06..89c2479 100644
--- a/opcodes/epiphany-dis.c
+++ b/opcodes/epiphany-dis.c
@@ -537,7 +537,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Default value for CGEN_PRINT_INSN.
The result is the size of the insn in bytes or zero for an unknown insn
- or -1 if an error occured fetching bytes. */
+ or -1 if an error occurred fetching bytes. */
#ifndef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN default_print_insn
diff --git a/opcodes/fr30-asm.c b/opcodes/fr30-asm.c
index 5c5871b..979c06c 100644
--- a/opcodes/fr30-asm.c
+++ b/opcodes/fr30-asm.c
@@ -597,7 +597,7 @@ parse_insn_normal (CGEN_CPU_DESC cd,
still needs to be converted to target byte order, otherwise BUF is an array
of bytes in target byte order.
The result is a pointer to the insn's entry in the opcode table,
- or NULL if an error occured (an error message will have already been
+ or NULL if an error occurred (an error message will have already been
printed).
Note that when processing (non-alias) macro-insns,
diff --git a/opcodes/fr30-dis.c b/opcodes/fr30-dis.c
index 77ddb50..9761a52 100644
--- a/opcodes/fr30-dis.c
+++ b/opcodes/fr30-dis.c
@@ -558,7 +558,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Default value for CGEN_PRINT_INSN.
The result is the size of the insn in bytes or zero for an unknown insn
- or -1 if an error occured fetching bytes. */
+ or -1 if an error occurred fetching bytes. */
#ifndef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN default_print_insn
diff --git a/opcodes/frv-asm.c b/opcodes/frv-asm.c
index 05df62d..65c8664 100644
--- a/opcodes/frv-asm.c
+++ b/opcodes/frv-asm.c
@@ -1550,7 +1550,7 @@ parse_insn_normal (CGEN_CPU_DESC cd,
still needs to be converted to target byte order, otherwise BUF is an array
of bytes in target byte order.
The result is a pointer to the insn's entry in the opcode table,
- or NULL if an error occured (an error message will have already been
+ or NULL if an error occurred (an error message will have already been
printed).
Note that when processing (non-alias) macro-insns,
diff --git a/opcodes/frv-dis.c b/opcodes/frv-dis.c
index 663ce36..708e1e6 100644
--- a/opcodes/frv-dis.c
+++ b/opcodes/frv-dis.c
@@ -655,7 +655,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Default value for CGEN_PRINT_INSN.
The result is the size of the insn in bytes or zero for an unknown insn
- or -1 if an error occured fetching bytes. */
+ or -1 if an error occurred fetching bytes. */
#ifndef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN default_print_insn
diff --git a/opcodes/frv-opc.c b/opcodes/frv-opc.c
index 2aed2f6..3b4e513 100644
--- a/opcodes/frv-opc.c
+++ b/opcodes/frv-opc.c
@@ -441,7 +441,7 @@ match_vliw (VLIW_COMBO *vliw1, VLIW_COMBO *vliw2, int vliw_size)
return TRUE;
}
-/* Find the next vliw vliw in the table that can accomodate the new insn.
+/* Find the next vliw vliw in the table that can accommodate the new insn.
If one is found then return it. Otherwise return NULL. */
static VLIW_COMBO *
diff --git a/opcodes/hppa-dis.c b/opcodes/hppa-dis.c
index 6b3dcde..38e57a6 100644
--- a/opcodes/hppa-dis.c
+++ b/opcodes/hppa-dis.c
@@ -49,7 +49,7 @@ static const char *const fp_reg_names[] =
typedef unsigned int CORE_ADDR;
-/* Get at various relevent fields of an instruction word. */
+/* Get at various relevant fields of an instruction word. */
#define MASK_5 0x1f
#define MASK_10 0x3ff
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 5f49f91..1ebae7a 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -610,7 +610,7 @@ enum
/* Static rounding. */
evex_rounding_mode,
- /* Supress all exceptions. */
+ /* Suppress all exceptions. */
evex_sae_mode,
/* Mask register operand. */
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index ba04ce4..bd4d844 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -556,7 +556,7 @@ enum
/* Static rounding control is supported. */
StaticRounding,
- /* Supress All Exceptions is supported. */
+ /* Suppress All Exceptions is supported. */
SAE,
/* Copressed Disp8*N attribute. */
diff --git a/opcodes/ip2k-asm.c b/opcodes/ip2k-asm.c
index 571f596..4396ea7 100644
--- a/opcodes/ip2k-asm.c
+++ b/opcodes/ip2k-asm.c
@@ -798,7 +798,7 @@ parse_insn_normal (CGEN_CPU_DESC cd,
still needs to be converted to target byte order, otherwise BUF is an array
of bytes in target byte order.
The result is a pointer to the insn's entry in the opcode table,
- or NULL if an error occured (an error message will have already been
+ or NULL if an error occurred (an error message will have already been
printed).
Note that when processing (non-alias) macro-insns,
diff --git a/opcodes/ip2k-dis.c b/opcodes/ip2k-dis.c
index 00b7150..5ed3e5f 100644
--- a/opcodes/ip2k-dis.c
+++ b/opcodes/ip2k-dis.c
@@ -547,7 +547,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Default value for CGEN_PRINT_INSN.
The result is the size of the insn in bytes or zero for an unknown insn
- or -1 if an error occured fetching bytes. */
+ or -1 if an error occurred fetching bytes. */
#ifndef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN default_print_insn
diff --git a/opcodes/iq2000-asm.c b/opcodes/iq2000-asm.c
index 9cd4a87..19d221f 100644
--- a/opcodes/iq2000-asm.c
+++ b/opcodes/iq2000-asm.c
@@ -746,7 +746,7 @@ parse_insn_normal (CGEN_CPU_DESC cd,
still needs to be converted to target byte order, otherwise BUF is an array
of bytes in target byte order.
The result is a pointer to the insn's entry in the opcode table,
- or NULL if an error occured (an error message will have already been
+ or NULL if an error occurred (an error message will have already been
printed).
Note that when processing (non-alias) macro-insns,
diff --git a/opcodes/iq2000-dis.c b/opcodes/iq2000-dis.c
index 540cdce..499a4ed 100644
--- a/opcodes/iq2000-dis.c
+++ b/opcodes/iq2000-dis.c
@@ -448,7 +448,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Default value for CGEN_PRINT_INSN.
The result is the size of the insn in bytes or zero for an unknown insn
- or -1 if an error occured fetching bytes. */
+ or -1 if an error occurred fetching bytes. */
#ifndef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN default_print_insn
diff --git a/opcodes/lm32-asm.c b/opcodes/lm32-asm.c
index 416236c..765807b 100644
--- a/opcodes/lm32-asm.c
+++ b/opcodes/lm32-asm.c
@@ -636,7 +636,7 @@ parse_insn_normal (CGEN_CPU_DESC cd,
still needs to be converted to target byte order, otherwise BUF is an array
of bytes in target byte order.
The result is a pointer to the insn's entry in the opcode table,
- or NULL if an error occured (an error message will have already been
+ or NULL if an error occurred (an error message will have already been
printed).
Note that when processing (non-alias) macro-insns,
diff --git a/opcodes/lm32-dis.c b/opcodes/lm32-dis.c
index c25f412..d269efb 100644
--- a/opcodes/lm32-dis.c
+++ b/opcodes/lm32-dis.c
@@ -406,7 +406,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Default value for CGEN_PRINT_INSN.
The result is the size of the insn in bytes or zero for an unknown insn
- or -1 if an error occured fetching bytes. */
+ or -1 if an error occurred fetching bytes. */
#ifndef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN default_print_insn
diff --git a/opcodes/m32c-asm.c b/opcodes/m32c-asm.c
index 61c6802..2a31e6a 100644
--- a/opcodes/m32c-asm.c
+++ b/opcodes/m32c-asm.c
@@ -1871,7 +1871,7 @@ parse_insn_normal (CGEN_CPU_DESC cd,
still needs to be converted to target byte order, otherwise BUF is an array
of bytes in target byte order.
The result is a pointer to the insn's entry in the opcode table,
- or NULL if an error occured (an error message will have already been
+ or NULL if an error occurred (an error message will have already been
printed).
Note that when processing (non-alias) macro-insns,
diff --git a/opcodes/m32c-dis.c b/opcodes/m32c-dis.c
index 37a5ad1..40b0828 100644
--- a/opcodes/m32c-dis.c
+++ b/opcodes/m32c-dis.c
@@ -1150,7 +1150,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Default value for CGEN_PRINT_INSN.
The result is the size of the insn in bytes or zero for an unknown insn
- or -1 if an error occured fetching bytes. */
+ or -1 if an error occurred fetching bytes. */
#ifndef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN default_print_insn
diff --git a/opcodes/m32r-asm.c b/opcodes/m32r-asm.c
index 78f905a..f7e9c9b 100644
--- a/opcodes/m32r-asm.c
+++ b/opcodes/m32r-asm.c
@@ -615,7 +615,7 @@ parse_insn_normal (CGEN_CPU_DESC cd,
still needs to be converted to target byte order, otherwise BUF is an array
of bytes in target byte order.
The result is a pointer to the insn's entry in the opcode table,
- or NULL if an error occured (an error message will have already been
+ or NULL if an error occurred (an error message will have already been
printed).
Note that when processing (non-alias) macro-insns,
diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c
index 35057d5..ddfcd2a 100644
--- a/opcodes/m32r-dis.c
+++ b/opcodes/m32r-dis.c
@@ -538,7 +538,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Default value for CGEN_PRINT_INSN.
The result is the size of the insn in bytes or zero for an unknown insn
- or -1 if an error occured fetching bytes. */
+ or -1 if an error occurred fetching bytes. */
#ifndef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN default_print_insn
diff --git a/opcodes/m68hc11-opc.c b/opcodes/m68hc11-opc.c
index eee565a..6ca959f 100644
--- a/opcodes/m68hc11-opc.c
+++ b/opcodes/m68hc11-opc.c
@@ -1707,7 +1707,7 @@ const struct m68hc11_opcode m68hc11_opcodes[] = {
{ "sub", M68XG_OP_R_IMM16, 2, 0xc000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
{ "cmp", M68XG_OP_R_IMM16, 2, 0xd000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
{ "add", M68XG_OP_R_IMM16, 2, 0xe000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
- /* ld is for backwards compatability only, the correct opcode is ldw */
+ /* ld is for backwards compatibility only, the correct opcode is ldw */
{ "ld", M68XG_OP_R_IMM16, 2, 0xf000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
{ "ldw", M68XG_OP_R_IMM16, 2, 0xf000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 }
};
diff --git a/opcodes/m68k-dis.c b/opcodes/m68k-dis.c
index 1e7c830..76d0a66 100644
--- a/opcodes/m68k-dis.c
+++ b/opcodes/m68k-dis.c
@@ -42,7 +42,7 @@ static char *const reg_names[] =
};
/* Name of register halves for MAC/EMAC.
- Seperate from reg_names since 'spu', 'fpl' look weird. */
+ Separate from reg_names since 'spu', 'fpl' look weird. */
static char *const reg_half_names[] =
{
"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
diff --git a/opcodes/m68k-opc.c b/opcodes/m68k-opc.c
index dc07f72..e678e62 100644
--- a/opcodes/m68k-opc.c
+++ b/opcodes/m68k-opc.c
@@ -1517,7 +1517,7 @@ const struct m68k_opcode m68k_opcodes[] =
/* NOTE: The mcf5200 family programmer's reference manual does not
indicate the byte form of the movea instruction is invalid (as it
- is on 68000 family cpus). However, experiments on the 5202 yeild
+ is on 68000 family cpus). However, experiments on the 5202 yield
unexpected results. The value is copied, but it is not sign extended
(as is done with movea.w) and the top three bytes in the address
register are not disturbed. I don't know if this is the intended
diff --git a/opcodes/mep-asm.c b/opcodes/mep-asm.c
index 89116ee..0c1559a 100644
--- a/opcodes/mep-asm.c
+++ b/opcodes/mep-asm.c
@@ -1574,7 +1574,7 @@ parse_insn_normal (CGEN_CPU_DESC cd,
still needs to be converted to target byte order, otherwise BUF is an array
of bytes in target byte order.
The result is a pointer to the insn's entry in the opcode table,
- or NULL if an error occured (an error message will have already been
+ or NULL if an error occurred (an error message will have already been
printed).
Note that when processing (non-alias) macro-insns,
diff --git a/opcodes/mep-dis.c b/opcodes/mep-dis.c
index 14ddb2e..1c926d9 100644
--- a/opcodes/mep-dis.c
+++ b/opcodes/mep-dis.c
@@ -357,7 +357,7 @@ mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
cop1buflength = 2;
}
- /* Now we have the distrubution set. Print them out. */
+ /* Now we have the distribution set. Print them out. */
status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength,
cop1buflength, cop2buflength);
@@ -446,7 +446,7 @@ mep_examine_vliw64_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
cop1buflength = 6;
}
- /* Now we have the distrubution set. Print them out. */
+ /* Now we have the distribution set. Print them out. */
status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength,
cop1buflength, cop2buflength);
@@ -1446,7 +1446,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Default value for CGEN_PRINT_INSN.
The result is the size of the insn in bytes or zero for an unknown insn
- or -1 if an error occured fetching bytes. */
+ or -1 if an error occurred fetching bytes. */
#ifndef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN default_print_insn
diff --git a/opcodes/metag-dis.c b/opcodes/metag-dis.c
index 1fdd43d..b6b3d14 100644
--- a/opcodes/metag-dis.c
+++ b/opcodes/metag-dis.c
@@ -2700,7 +2700,7 @@ print_dalu (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
decode_template_definition (insn_word, buf + len,
OPERAND_WIDTH - len);
}
- else /* Not a template definiton. */
+ else /* Not a template definition. */
{
reg_nums[0] = ((insn_word >> 19) & REG_MASK);
reg_nums[1] = ((insn_word >> 14) & REG_MASK);
diff --git a/opcodes/msp430-decode.c b/opcodes/msp430-decode.c
index 137205f..758f3aa 100644
--- a/opcodes/msp430-decode.c
+++ b/opcodes/msp430-decode.c
@@ -347,7 +347,7 @@ msp430_decode_opcode (unsigned long pc,
post_extension_word:
;
- /* 430X extention word. */
+ /* 430X extension word. */
GETBYTE ();
switch (op[0] & 0xff)
{
diff --git a/opcodes/msp430-dis.c b/opcodes/msp430-dis.c
index c057c9b..ae0f4f7 100644
--- a/opcodes/msp430-dis.c
+++ b/opcodes/msp430-dis.c
@@ -136,7 +136,7 @@ msp430_nooperands (struct msp430_opcode_s *opcode,
}
else
{
- strcpy (comm, "return from interupt");
+ strcpy (comm, "return from interrupt");
*cycles = 5;
}
diff --git a/opcodes/mt-asm.c b/opcodes/mt-asm.c
index 87e9d6f..d40c11c 100644
--- a/opcodes/mt-asm.c
+++ b/opcodes/mt-asm.c
@@ -882,7 +882,7 @@ parse_insn_normal (CGEN_CPU_DESC cd,
still needs to be converted to target byte order, otherwise BUF is an array
of bytes in target byte order.
The result is a pointer to the insn's entry in the opcode table,
- or NULL if an error occured (an error message will have already been
+ or NULL if an error occurred (an error message will have already been
printed).
Note that when processing (non-alias) macro-insns,
diff --git a/opcodes/mt-dis.c b/opcodes/mt-dis.c
index e049d20..201b649 100644
--- a/opcodes/mt-dis.c
+++ b/opcodes/mt-dis.c
@@ -549,7 +549,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Default value for CGEN_PRINT_INSN.
The result is the size of the insn in bytes or zero for an unknown insn
- or -1 if an error occured fetching bytes. */
+ or -1 if an error occurred fetching bytes. */
#ifndef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN default_print_insn
diff --git a/opcodes/ns32k-dis.c b/opcodes/ns32k-dis.c
index b14d5d7..bc831bb 100644
--- a/opcodes/ns32k-dis.c
+++ b/opcodes/ns32k-dis.c
@@ -347,7 +347,7 @@ flip_bytes (char *ptr, int count)
((c) == 'F' || (c) == 'L' || (c) == 'B' \
|| (c) == 'W' || (c) == 'D' || (c) == 'A' || (c) == 'I' || (c) == 'Z')
-/* Adressing modes. */
+/* Addressing modes. */
#define Adrmod_index_byte 0x1c
#define Adrmod_index_word 0x1d
#define Adrmod_index_doubleword 0x1e
diff --git a/opcodes/opintl.h b/opcodes/opintl.h
index 3d811bd..8dad5b2 100644
--- a/opcodes/opintl.h
+++ b/opcodes/opintl.h
@@ -26,7 +26,7 @@
This is because the code in this directory is used to build a library which
will be linked with code in other directories to form programs. We want to
- maintain a seperate translation file for this directory however, rather
+ maintain a separate translation file for this directory however, rather
than being forced to merge it with that of any program linked to
libopcodes. This is a library, so it cannot depend on the catalog
currently loaded.
diff --git a/opcodes/or1k-asm.c b/opcodes/or1k-asm.c
index 91c8136..9902f09 100644
--- a/opcodes/or1k-asm.c
+++ b/opcodes/or1k-asm.c
@@ -790,7 +790,7 @@ parse_insn_normal (CGEN_CPU_DESC cd,
still needs to be converted to target byte order, otherwise BUF is an array
of bytes in target byte order.
The result is a pointer to the insn's entry in the opcode table,
- or NULL if an error occured (an error message will have already been
+ or NULL if an error occurred (an error message will have already been
printed).
Note that when processing (non-alias) macro-insns,
diff --git a/opcodes/or1k-desc.h b/opcodes/or1k-desc.h
index 1ffc0f4..a0cb50b 100644
--- a/opcodes/or1k-desc.h
+++ b/opcodes/or1k-desc.h
@@ -73,7 +73,7 @@ typedef enum spr_groups {
, SPR_GROUP_POWER, SPR_GROUP_PIC, SPR_GROUP_TICK, SPR_GROUP_FPU
} SPR_GROUPS;
-/* Enum declaration for special purpose register indicies. */
+/* Enum declaration for special purpose register indices. */
typedef enum spr_reg_indices {
SPR_INDEX_SYS_VR = 0, SPR_INDEX_SYS_UPR = 1, SPR_INDEX_SYS_CPUCFGR = 2, SPR_INDEX_SYS_DMMUCFGR = 3
, SPR_INDEX_SYS_IMMUCFGR = 4, SPR_INDEX_SYS_DCCFGR = 5, SPR_INDEX_SYS_ICCFGR = 6, SPR_INDEX_SYS_DCFGR = 7
diff --git a/opcodes/or1k-dis.c b/opcodes/or1k-dis.c
index 65a3b32..0f02122 100644
--- a/opcodes/or1k-dis.c
+++ b/opcodes/or1k-dis.c
@@ -400,7 +400,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Default value for CGEN_PRINT_INSN.
The result is the size of the insn in bytes or zero for an unknown insn
- or -1 if an error occured fetching bytes. */
+ or -1 if an error occurred fetching bytes. */
#ifndef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN default_print_insn
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 8c59033..a364dc4 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -416,7 +416,7 @@ const struct powerpc_operand powerpc_operands[] =
#define FXM4 FXM + 1
{ 0xff, 12, insert_fxm, extract_fxm,
PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
- /* If the FXM4 operand is ommitted, use the sentinel value -1. */
+ /* If the FXM4 operand is omitted, use the sentinel value -1. */
{ -1, -1, NULL, NULL, 0},
/* The IMM20 field in an LI instruction. */
@@ -705,7 +705,7 @@ const struct powerpc_operand powerpc_operands[] =
#define TBR SV + 1
{ 0x3ff, 11, insert_tbr, extract_tbr,
PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
- /* If the TBR operand is ommitted, use the value 268. */
+ /* If the TBR operand is omitted, use the value 268. */
{ -1, 268, NULL, NULL, 0},
/* The TO field in a D or X form instruction. */
@@ -845,7 +845,7 @@ const struct powerpc_operand powerpc_operands[] =
/* The S field in a XL form instruction. */
#define SXL S + 1
{ 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
- /* If the SXL operand is ommitted, use the value 1. */
+ /* If the SXL operand is omitted, use the value 1. */
{ -1, 1, NULL, NULL, 0},
/* SH field starting at bit position 16. */
diff --git a/opcodes/sh-dis.c b/opcodes/sh-dis.c
index 7af514b..f2e193f 100644
--- a/opcodes/sh-dis.c
+++ b/opcodes/sh-dis.c
@@ -399,7 +399,7 @@ print_insn_sh (bfd_vma memaddr, struct disassemble_info *info)
target_arch = arch_sh1;
/* SH coff object files lack information about the machine type, so
we end up with bfd_mach_sh unless it was set explicitly (which
- could have happended if this is a call from gdb or the simulator.) */
+ could have happened if this is a call from gdb or the simulator.) */
if (info->symbols
&& bfd_asymbol_flavour(*info->symbols) == bfd_target_coff_flavour)
target_arch = arch_sh4;
diff --git a/opcodes/sh64-dis.c b/opcodes/sh64-dis.c
index e29a4e0..b8da0b8 100644
--- a/opcodes/sh64-dis.c
+++ b/opcodes/sh64-dis.c
@@ -44,7 +44,7 @@ struct sh64_disassemble_info
unsigned int address_reg;
bfd_signed_vma built_address;
- /* This is the range decriptor for the current address. It is kept
+ /* This is the range descriptor for the current address. It is kept
around for the next call. */
sh64_elf_crange crange;
};
diff --git a/opcodes/tic30-dis.c b/opcodes/tic30-dis.c
index 614da14..07b25f9 100644
--- a/opcodes/tic30-dis.c
+++ b/opcodes/tic30-dis.c
@@ -687,7 +687,7 @@ print_insn_tic30 (bfd_vma pc, disassemble_info *info)
insn_word = (*(info->buffer + bufaddr) << 24) | (*(info->buffer + bufaddr + 1) << 16) |
(*(info->buffer + bufaddr + 2) << 8) | *(info->buffer + bufaddr + 3);
_pc = pc / 4;
- /* Get the instruction refered to by the current instruction word
+ /* Get the instruction referred to by the current instruction word
and print it out based on its type. */
if (!get_tic30_instruction (insn_word, &insn))
return -1;
diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c
index d5e54a5..b1d47d3 100644
--- a/opcodes/v850-opc.c
+++ b/opcodes/v850-opc.c
@@ -1329,7 +1329,7 @@ const struct v850_operand v850_operands[] =
sorted by major opcode.
The table is also sorted by name. This is used by the assembler.
- When parsing an instruction the assembler finds the first occurance
+ When parsing an instruction the assembler finds the first occurrence
of the name of the instruciton in this table and then attempts to
match the instruction's arguments with description of the operands
associated with the entry it has just found in this table. If the
diff --git a/opcodes/xc16x-asm.c b/opcodes/xc16x-asm.c
index 509cbaa..ffb114c 100644
--- a/opcodes/xc16x-asm.c
+++ b/opcodes/xc16x-asm.c
@@ -663,7 +663,7 @@ parse_insn_normal (CGEN_CPU_DESC cd,
still needs to be converted to target byte order, otherwise BUF is an array
of bytes in target byte order.
The result is a pointer to the insn's entry in the opcode table,
- or NULL if an error occured (an error message will have already been
+ or NULL if an error occurred (an error message will have already been
printed).
Note that when processing (non-alias) macro-insns,
diff --git a/opcodes/xc16x-dis.c b/opcodes/xc16x-dis.c
index c8e67d4..951cb2e 100644
--- a/opcodes/xc16x-dis.c
+++ b/opcodes/xc16x-dis.c
@@ -679,7 +679,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Default value for CGEN_PRINT_INSN.
The result is the size of the insn in bytes or zero for an unknown insn
- or -1 if an error occured fetching bytes. */
+ or -1 if an error occurred fetching bytes. */
#ifndef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN default_print_insn
diff --git a/opcodes/xstormy16-asm.c b/opcodes/xstormy16-asm.c
index bd91d82..f74a98a 100644
--- a/opcodes/xstormy16-asm.c
+++ b/opcodes/xstormy16-asm.c
@@ -563,7 +563,7 @@ parse_insn_normal (CGEN_CPU_DESC cd,
still needs to be converted to target byte order, otherwise BUF is an array
of bytes in target byte order.
The result is a pointer to the insn's entry in the opcode table,
- or NULL if an error occured (an error message will have already been
+ or NULL if an error occurred (an error message will have already been
printed).
Note that when processing (non-alias) macro-insns,
diff --git a/opcodes/xstormy16-dis.c b/opcodes/xstormy16-dis.c
index 2c273d4..df9f36b 100644
--- a/opcodes/xstormy16-dis.c
+++ b/opcodes/xstormy16-dis.c
@@ -427,7 +427,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Default value for CGEN_PRINT_INSN.
The result is the size of the insn in bytes or zero for an unknown insn
- or -1 if an error occured fetching bytes. */
+ or -1 if an error occurred fetching bytes. */
#ifndef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN default_print_insn
diff --git a/opcodes/xtensa-dis.c b/opcodes/xtensa-dis.c
index db3bbee..27de320 100644
--- a/opcodes/xtensa-dis.c
+++ b/opcodes/xtensa-dis.c
@@ -160,7 +160,7 @@ print_insn_xtensa (bfd_vma memaddr, struct disassemble_info *info)
an 80-column screen.) The value of bytes_per_line here is not exactly
right, because objdump adds an extra space for each chunk so that the
amount of whitespace depends on the chunk size. Oh well, it's good
- enough.... Note that we set the minimum size to 4 to accomodate
+ enough.... Note that we set the minimum size to 4 to accommodate
literal pools. */
info->bytes_per_line = MAX (maxsize, 4);
--
2.7.4