[PATCH] arm reversible <phase_2_complete>

[oza Pawandeep <oza dot pawandeep at gmail dot com>]

Hi,

I am working on phase-3 now.
if anybody could please start reviewing phase-2 patch (as this is
independent of phase-3 and could be checked in independently too)
I may start implementing review comments as and when I get.
In Parallel, test cases are also being worked upon.
following is the phase-2 patch.

PATCH STARTS.
------------------------------
diff -urN arm_orig/arm-linux-tdep.c arm_new/arm-linux-tdep.c
--- arm_orig/arm-linux-tdep.c  Â2011-03-03 09:21:13.000000000 +0530
+++ arm_new/arm-linux-tdep.c  Â2011-04-15 13:11:15.000000000 +0530
@@ -998,6 +998,9 @@
 set_gdbarch_fetch_tls_load_module_address (gdbarch,
                      Âsvr4_fetch_objfile_link_map);

+ Â/* Enable process record */
+ Âset_gdbarch_process_record(gdbarch, arm_process_record);
+
 tramp_frame_prepend_unwinder (gdbarch,
        &arm_linux_sigreturn_tramp_frame);
 tramp_frame_prepend_unwinder (gdbarch,
@@ -1025,6 +1028,8 @@


 tdep->syscall_next_pc = arm_linux_syscall_next_pc;
+
+ Âtdep->arm_swi_record = NULL;
Â}

Â/* Provide a prototype to silence -Wmissing-prototypes. Â*/
diff -urN arm_orig/arm-tdep.c arm_new/arm-tdep.c
--- arm_orig/arm-tdep.c  Â2011-03-03 09:21:13.000000000 +0530
+++ arm_new/arm-tdep.c  Â2011-04-15 13:11:15.000000000 +0530
@@ -54,8 +54,11 @@
Â#include "gdb_assert.h"
Â#include "vec.h"

+#include "record.h"
+
Â#include "features/arm-with-m.c"

+
Âstatic int arm_debug;

Â/* Macros for setting and testing a bit in a minimal symbol that marks
@@ -7929,3 +7932,1692 @@
       ÂNULL, /* FIXME: i18n: "ARM debugging is %s. Â*/
       Â&setdebuglist, &showdebuglist);
Â}
+
+
+
+/* arm-reversible process reacord data structures. Â*/
+
+#define ARM_INSN_SIZE_BYTES 4
+#define THUMB_INSN_SIZE_BYTES 2
+#define THUMB2_INSN_SIZE_BYTES 4
+#define NO_OF_TYPE_OF_ARM_INSNS 8
+#define NO_OF_TYPE_OF_THUMB_INSNS 8
+#define ARM_RECORD_ARCH_LIST_ADD_REG(regnum) \
+ Â Ârecord_arch_list_add_reg (arm_record.regcache, regnum)
+#define GET_REG_VAL(REGCACHE,NO,BUF) Âregcache_raw_read (REGCACHE, NO, BUF);
+#define INSN_S_L_BIT_NUM 20
+
+struct arm_mem_r
+{
+ Â Âuint32_t len;
+ Â ÂCORE_ADDR addr;
+};
+
+typedef struct insn_decode_record_t
+{
+ Âstruct gdbarch *gdbarch;
+ Âstruct regcache *regcache;
+ ÂCORE_ADDR this_addr; Â Â Â Â Â/* address of the insn being decoded. Â*/
+ Âuint32_t arm_insn; Â Â Â Â Â Â/* should accomodate thumb. Â*/
+ Âuint32_t cond; Â Â Â Â Â Â Â Â/* condition code. Â*/
+ Âuint32_t id; Â Â Â Â Â Â Â Â Â/* type of insn. Â*/
+ Âuint32_t opcode; Â Â Â Â Â Â Â/* insn opcode. Â*/
+ Âuint32_t decode; Â Â Â Â Â Â Â/* insn decode bits. Â*/
+ Âuint32_t *arm_regs; Â Â Â Â Â /* registers to be saved for this record. Â*/
+ Âstruct arm_mem_r *arm_mems; Â /* memory to be saved for this record. Â*/
+} insn_decode_record;
+
+
+static int
+SBO_SBZ (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo)
+{
+ Âuint32_t ONES = bits (insn, bit_num - 1, (bit_num -1) + (len - 1));
+
+ Âif (!len)
+ Â Âreturn 1;
+
+ Âif(!sbo)
+ Â ÂONES = ~ONES;
+
+ Âwhile (ONES)
+ Â Â{
+ Â Â Âif (!(ONES & sbo))
+ Â Â Â Â{
+ Â Â Â Â Âreturn 0;
+ Â Â Â Â}
+ Â Â ÂONES = ONES >> 1;
+ Â Â}
+ Âreturn 1;
+}
+
+static int
+handle_extension_space (insn_decode_record *arm_record)
+{
+ Âinsn_decode_record *arm_insn_r = arm_record;
+ Âstruct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch);
+ Âstruct regcache *reg_cache = arm_insn_r->regcache;
+
+ Âuint32_t reg_src1 = 0, reg_src2 = 0;
+ Âuint32_t opcode1 = 0, opcode2 = 0;
+
+ Âopcode1 = bits (arm_insn_r->arm_insn, 25, 27);
+ Âif ((3 == opcode1) && (bit (arm_insn_r->arm_insn, 4)))
+ Â Â{
+ Â Â Â/* undefined instruction on ARM V5; need to handle if later versions
+ Â Â Â Â Âdefine it. Â*/
+ Â Â}
+
+ Âopcode2 = bits (arm_insn_r->arm_insn, 4, 7);
+
+ Âif ((!opcode1) && (9 == opcode2))
+ Â Â{
+ Â Â Â/* handle arithmetic insn extension space. Â*/
+ Â Â}
+
+ Âopcode1 = bits (arm_insn_r->arm_insn, 26, 27);
+ Âopcode2 = bits (arm_insn_r->arm_insn, 23, 24);
+
+ Âif ((!opcode1) && (2 == opcode2) && (!bit (arm_insn_r->arm_insn, 20)))
+ Â Â{
+ Â Â Â/* handle control insn extension space. Â*/
+ Â Â}
+
+ Âopcode1 = bits (arm_insn_r->arm_insn, 25, 27);
+ Âif ((!opcode1) && (bit (arm_insn_r->arm_insn, 7)) \
+ Â Â Â Â Â Â Â Â && (bit(arm_insn_r->arm_insn, 4)))
+ Â Â{
+ Â Â Â/* handle load/store insn extension space. Â*/
+ Â Â}
+
+ Âopcode1 = bits (arm_insn_r->arm_insn, 23, 27);
+ Âif ((24 == opcode1) && (bit (arm_insn_r->arm_insn, 21)))
+ Â Â{
+ Â Â Â/* handle coprocessor insn extension space. Â*/
+ Â Â}
+
+ Â/* to be done for ARMv5 and later; as of now we return -1. Â*/
+ Âreturn -1;
+}
+
+static int
+arm_handle_data_proc_misc_load_str_insn (void *data)
+{
+
+ Âinsn_decode_record *arm_insn_r = (insn_decode_record*) data;
+ Âstruct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch);
+ Âstruct regcache *reg_cache = arm_insn_r->regcache;
+
+ Âunion
+ Â Â{
+ Â Â Âuint32_t s_word;
+ Â Â Âgdb_byte buf[4];
+ Â Â} u_buf[2];
+
+
+ Âuint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
+ Âuint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
+ Âuint32_t opcode1 = 0;
+
+ Âmemset(&u_buf, 0, sizeof(u_buf));
+
+ Âarm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
+ Âarm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
+ Âopcode1 = bits (arm_insn_r->arm_insn, 20, 24);
+
+ Â/* data processing insn /multiply insn. Â*/
+ Âif ((9 == arm_insn_r->decode)
+ Â Â && (((4 <= arm_insn_r->opcode) && (7 >= arm_insn_r->opcode))
+ Â Â || Â((0 == arm_insn_r->opcode) || (1 == arm_insn_r->opcode))))
+ Â Â{
+ Â Â Â/* handle multiply instructions. Â*/
+ Â Â Â/* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. Â*/
+ Â Â Â Âif ((0 == arm_insn_r->opcode) || (1 == arm_insn_r->opcode))
+ Â Â Â Â Â{
+ Â Â Â Â Â Â/* handle MLA and MUL. Â*/
+ Â Â Â Â Â Âarm_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*3);
+ Â Â Â Â Â Âarm_insn_r->arm_regs[0] = 2;
+ Â Â Â Â Â Âarm_insn_r->arm_regs[1] = bits (arm_insn_r->arm_insn, 16, 19);
+ Â Â Â Â Â Âarm_insn_r->arm_regs[2] = ARM_PS_REGNUM;
+ Â Â Â Â Â}
+ Â Â Â Âelse if ((4 <= arm_insn_r->opcode) && (7 >= arm_insn_r->opcode))
+ Â Â Â Â {
+ Â Â Â Â Â/* handle SMLAL, SMULL, UMLAL, UMULL. Â*/
+ Â Â Â Â Â arm_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*4);
+ Â Â Â Â Â arm_insn_r->arm_regs[0] = 3;
+ Â Â Â Â Â arm_insn_r->arm_regs[1] = bits (arm_insn_r->arm_insn, 16, 19);
+ Â Â Â Â Â arm_insn_r->arm_regs[2] = bits (arm_insn_r->arm_insn, 12, 15);
+ Â Â Â Â Â arm_insn_r->arm_regs[3] = ARM_PS_REGNUM;
+ Â Â Â Â }
+ Â Â Â}
+ Âelse if ((bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
+ Â Â Â Â&& ((11 == arm_insn_r->decode) || (13 == arm_insn_r->decode)))
+ Â Â Â{
+ Â Â Â Â/* handle misc load insns, as 20th bit (L = 1). Â*/
+ Â Â Â Â/* LDR insn has a capability to do branching, if
+ Â Â Â Â Â Â Â Â ÂMOV LR, PC is precedded by LDR insn having Rn as R15
+ Â Â Â Â Â Â Â Â Âin that case, it emulates branch and link insn, and hence we
+ Â Â Â Â Â Â Â Â Âneed to save CSPR and PC as well. I am not sure this is right

+ Â Â Â Â Â Â Â Â Âplace as opcode = 010 LDR insn make this happen, if R15 was
+ Â Â Â Â Â Â Â Â Âused. Â*/
+ Â Â Â Âreg_dest = bits (arm_insn_r->arm_insn, 12, 15);
+ Â Â Â Âif (15 != reg_dest)
+ Â Â Â Â Â{
+ Â Â Â Â Â Âarm_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*2);
+ Â Â Â Â Â Âarm_insn_r->arm_regs[0] = 1;
+ Â Â Â Â Â Âarm_insn_r->arm_regs[1] = bits (arm_insn_r->arm_insn, 12, 15);
+ Â Â Â Â Â}
+ Â Â Â Âelse
+ Â Â Â Â Â{
+ Â Â Â Â Â Âarm_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*3);
+ Â Â Â Â Â Âarm_insn_r->arm_regs[0] = 2;
+ Â Â Â Â Â Âarm_insn_r->arm_regs[1] = reg_dest;
+ Â Â Â Â Â Âarm_insn_r->arm_regs[2] = ARM_PS_REGNUM;
+ Â Â Â Â Â}
+ Â Â Â}
+ Âelse if (((9 == arm_insn_r->opcode) || (11 == arm_insn_r->opcode))
+ Â Â Â&& (SBO_SBZ (arm_insn_r->arm_insn, 5, 12, 0))
+ Â Â Â&& (SBO_SBZ (arm_insn_r->arm_insn, 13, 4, 1))
+ Â Â Â&& (2 == bits (arm_insn_r->arm_insn, 20, 21)))
+ Â Â{
+ Â Â Â/* handle MSR insn. Â*/
+ Â Â Âarm_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*2);
+ Â Â Âif (9 == arm_insn_r->opcode)
+ Â Â Â Â{
+ Â Â Â Â Â/* CSPR is going to be changed. Â*/
+ Â Â Â Â Âarm_insn_r->arm_regs[0] = 1;
+ Â Â Â Â Âarm_insn_r->arm_regs[1] = ARM_PS_REGNUM;
+ Â Â Â Â}
+ Â Â Âelse
+ Â Â Â{
+ Â Â Â Â/* SPSR is going to be changed. */
+ Â Â Â Â/* Oza: FIX ME ? how to read SPSR value ? Â*/
+ Â Â Â}
+ Â Â}
+ Âelse if ((9 == arm_insn_r->decode)
+ Â Â Â Â Â && ((8 == arm_insn_r->opcode) || (10 == arm_insn_r->opcode))
+ Â Â Â Â Â && (!bit (arm_insn_r->arm_insn, ÂINSN_S_L_BIT_NUM)))
+ Â Â{
+ Â Â Â/* Handling SWP, SWPB. Â*/
+ Â Â Â/* these insns, changes register and memory as well. Â*/
+ Â Â Â/* SWP or SWPB insn. Â*/
+ Â Â Âarm_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*2);
+ Â Â Âarm_insn_r->arm_mems = (struct arm_mem_r *)xmalloc (sizeof(struct
+ Â Â Â Â Â Â Â Â Â Â Â Â Â Â Âarm_mem_r)*2);
+ Â Â Â/* get memory address given by Rn. Â*/
+ Â Â Âreg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
+ Â Â ÂGET_REG_VAL (reg_cache, reg_src1, &u_buf[0].buf[0]);
+ Â Â Âarm_insn_r->arm_mems[0].len = 1;
+ Â Â Â/* SWP insn ?, swaps word. Â*/
+ Â Â Âif (8 == arm_insn_r->opcode)
+ Â Â Â Â{
+ Â Â Â Â Âarm_insn_r->arm_mems[1].len = 4;
+ Â Â Â Â}
+ Â Â Â Âelse
+ Â Â Â Â{
+ Â Â Â Â Â/* SWPB insn, swaps only byte. Â*/
+ Â Â Â Â Âarm_insn_r->arm_mems[1].len = 1;
+ Â Â Â Â}
+ Â Â Âarm_insn_r->arm_mems[1].addr = u_buf[0].s_word;
+ Â Â Âarm_insn_r->arm_regs[0] = 1;
+ Â Â Âarm_insn_r->arm_regs[1] = bits (arm_insn_r->arm_insn, 12, 15);
+ Â Â}
+ Âelse if ((3 == arm_insn_r->decode) && (0x12 == opcode1)
+ Â Â Â Â Â && (SBO_SBZ (arm_insn_r->arm_insn, 9, 12, 1)))
+ Â Â{
+ Â Â Â/* handle BLX, branch and link/exchange. Â*/
+ Â Â Âif (9 == arm_insn_r->opcode)
+ Â Â Â{
+ Â Â Â Â/* branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
+ Â Â Â Â Â Â Â Â Â Â and R14 stores the return address. Â*/
+ Â Â Â Âarm_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*3);
+ Â Â Â Âarm_insn_r->arm_regs[0] = 2;
+ Â Â Â Âarm_insn_r->arm_regs[1] = ARM_PS_REGNUM;
+ Â Â Â Âarm_insn_r->arm_regs[2] = ARM_LR_REGNUM;
+ Â Â Â}
+ Â Â}
+ Âelse if ((7 == arm_insn_r->decode) && (0x12 == opcode1))
+ Â Â{
+ Â Â Â/* handle enhanced software breakpoint insn, BKPT */
+ Â Â Â/* CPSR is changed to be executed in ARM state, Âdisabling normal
+ Â Â Â Â Â Â Â interrupts, entering abort mode. Â*/
+ Â Â Â/* accorindly to high vector configuration PC is set accordingly */
+ Â Â Â/* Oza: FIX ME ? Âwhat if user hit breakpoint and type reverse, in
+ Â Â Â Â Â Â Â that case, we need to go back with previous CPSR and
+ Â Â Â Â Â Â Â Program Counter. Â*/
+ Â Â Âarm_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*3);
+ Â Â Âarm_insn_r->arm_regs[0] = 2;
+ Â Â Âarm_insn_r->arm_regs[1] = ARM_PS_REGNUM;
+ Â Â Âarm_insn_r->arm_regs[2] = ARM_LR_REGNUM;
+ Â Â Â/* save SPSR also; how? Â*/
+ Â Â}
+ Âelse if ((11 == arm_insn_r->decode)
+ Â Â Â Â Â&& (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)))
+ Â{
+ Â Â/* handle enhanced store insns and DSP insns (e.g. LDRD)
+ Â Â Â Â Â let us begin according to addressing modes for store insns
+ Â Â Â Â Â STRH insn, addresing modes are taken following. Â*/
+ Â Âif ((14 == arm_insn_r->opcode) || (10 == arm_insn_r->opcode))
+ Â Â Â{
+ Â Â Â Â/* 1) handle misc store, immediate offset. Â*/
+ Â Â Â Âprintf("handling store insn, immed offfset insn\n");
+ Â Â Â Âimmed_low = bits (arm_insn_r->arm_insn, 0, 3);
+ Â Â Â Âimmed_high = bits (arm_insn_r->arm_insn, 8, 11);
+ Â Â Â Âreg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
+ Â Â Â ÂGET_REG_VAL (reg_cache, reg_src1, &u_buf[0].buf[0]);
+ Â Â Â Âif (15 == reg_src1)
+ Â Â Â Â Â{
+ Â Â Â Â Â Â/* if R15 was used as Rn, hence current PC+8. Â*/
+ Â Â Â Â Â Âu_buf[0].s_word = u_buf[0].s_word + 8;
+ Â Â Â Â Â}
+ Â Â Â Âoffset_8 = (immed_high << 4) | immed_low;
+ Â Â Â Â/* calculate target store address. Â*/
+ Â Â Â Âif (14 == arm_insn_r->opcode)
+ Â Â Â Â Â{
+ Â Â Â Â Â Âtgt_mem_addr = u_buf[0].s_word + offset_8;
+ Â Â Â Â Â}
+ Â Â Â Âelse
+ Â Â Â Â Â{
+ Â Â Â Â Â Âtgt_mem_addr = u_buf[0].s_word - offset_8;
+ Â Â Â Â Â}
+ Â Â Â Âarm_insn_r->arm_mems = (struct arm_mem_r *)xmalloc (sizeof(struct
+ Â Â Â Âarm_mem_r)*2);
+ Â Â Â Âarm_insn_r->arm_mems[0].len = 1;
+ Â Â Â Âarm_insn_r->arm_mems[1].len = 2;
+ Â Â Â Âarm_insn_r->arm_mems[1].addr = tgt_mem_addr;
+ Â Â Â}
+ Â Âelse if ((12 == arm_insn_r->opcode) || (8 == arm_insn_r->opcode))
+ Â Â Â{
+ Â Â Â Â/* 2) store, register offset. Â*/
+ Â Â Â Â/* get Rm. Â*/
+ Â Â Â Âreg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
+ Â Â Â Â/* get Rn. Â*/
+ Â Â Â Âreg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
+ Â Â Â ÂGET_REG_VAL (reg_cache, reg_src1, &u_buf[0].buf[0]);
+ Â Â Â ÂGET_REG_VAL (reg_cache, reg_src2,
&u_buf[1].buf[0]);

+ Â Â Â Âif (15 == reg_src2)
+ Â Â Â Â Â{
+ Â Â Â Â Â Â/* if R15 was used as Rn, hence current PC+8. Â*/
+ Â Â Â Â Â Âu_buf[0].s_word = u_buf[0].s_word + 8;
+ Â Â Â Â Â}
+ Â Â Â Â/* calculate target store address, Rn +/- Rm, register offset. Â*/
+ Â Â Â Âif (12 == arm_insn_r->opcode)
+ Â Â Â Â Â{
+ Â Â Â Â Â Âtgt_mem_addr = u_buf[0].s_word + u_buf[1].s_word;
+ Â Â Â Â Â}
+ Â Â Â Âelse
+ Â Â Â Â Â{
+ Â Â Â Â Â Âtgt_mem_addr = u_buf[1].s_word - u_buf[0].s_word;
+ Â Â Â Â Â}
+ Â Â Â Âarm_insn_r->arm_mems = (struct arm_mem_r *)xmalloc (sizeof(struct
+ Â Â Â Âarm_mem_r)*2);
+ Â Â Â Âarm_insn_r->arm_mems[0].len = 1;
+ Â Â Â Âarm_insn_r->arm_mems[1].len = 2;
+ Â Â Â Âarm_insn_r->arm_mems[1].addr = tgt_mem_addr;
+ Â Â Â}
+ Â Âelse if ((11 == arm_insn_r->opcode) || (15 == arm_insn_r->opcode)
+ Â Â Â|| (2 == arm_insn_r->opcode) || (6 == arm_insn_r->opcode))
+ Â Â Â{
+ Â Â Â Â/* 3) store, immediate pre-indexed. Â*/
+ Â Â Â Â/* 5) Âstore, immediate post-indexed. Â*/
+ Â Â Â Âimmed_low = bits (arm_insn_r->arm_insn, 0, 3);
+ Â Â Â Âimmed_high = bits (arm_insn_r->arm_insn, 8, 11);
+ Â Â Â Âoffset_8 = (immed_high << 4) | immed_low;
+ Â Â Â Âreg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
+ Â Â Â ÂGET_REG_VAL(reg_cache, reg_src1, &u_buf[0].buf[0]);
+ Â Â Â Â/* calculate target store address, Rn +/- Rm, register offset. Â*/
+ Â Â Â Âif ((15 == arm_insn_r->opcode) || (6 == arm_insn_r->opcode))
+ Â Â Â Â Â{
+ Â Â Â Â Â Âtgt_mem_addr = u_buf[0].s_word + offset_8;
+ Â Â Â Â Â}
+ Â Â Â Âelse
+ Â Â Â Â Â{
+ Â Â Â Â Â Âtgt_mem_addr = u_buf[0].s_word - offset_8;
+ Â Â Â Â Â}
+ Â Â Â Âarm_insn_r->arm_mems = (struct arm_mem_r *)xmalloc (sizeof(struct
+ Â Â Â Âarm_mem_r)*2);
+ Â Â Â Âarm_insn_r->arm_mems[0].len = 1;
+ Â Â Â Âarm_insn_r->arm_mems[1].len = 2;
+ Â Â Â Âarm_insn_r->arm_mems[1].addr = tgt_mem_addr;
+ Â Â Â Â/* record Rn also as it changes. Â*/
+ Â Â Â Âarm_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*2);
+ Â Â Â Âarm_insn_r->arm_regs[0] = 1;
+ Â Â Â Âarm_insn_r->arm_regs[1] = bits (arm_insn_r->arm_insn, 16, 19);
+ Â Â Â}
+ Â Âelse if ((9 == arm_insn_r->opcode) || (13 == arm_insn_r->opcode)
+ Â Â Â|| (0 == arm_insn_r->opcode) || (4 == arm_insn_r->opcode))
+ Â Â Â{
+ Â Â Â Â/* 4) store, register pre-indexed. Â*/
+ Â Â Â Â/* 6) store, register post -indexed. Â*/
+ Â Â Â Âreg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
+ Â Â Â Âreg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
+ Â Â Â ÂGET_REG_VAL (reg_cache, reg_src1, &u_buf[0].buf[0]);
+ Â Â Â ÂGET_REG_VAL (reg_cache, reg_src2, &u_buf[1].buf[0]);
+ Â Â Â Â/* calculate target store address, Rn +/- Rm, register offset. Â*/
+ Â Â Â Âif ((13 == arm_insn_r->opcode) || (4 == arm_insn_r->opcode))
+ Â Â Â Â Â{
+ Â Â Â Â Â Âtgt_mem_addr = u_buf[0].s_word + u_buf[1].s_word;
+ Â Â Â Â Â}
+ Â Â Â Âelse
+ Â Â Â Â Â{
+ Â Â Â Â Â Âtgt_mem_addr = u_buf[1].s_word - u_buf[0].s_word;
+ Â Â Â Â Â}
+ Â Â Â Âarm_insn_r->arm_mems = (struct arm_mem_r *)xmalloc (sizeof(struct
+ Â Â Â Âarm_mem_r)*2);
+ Â Â Â Âarm_insn_r->arm_mems[0].len = 1;
+ Â Â Â Âarm_insn_r->arm_mems[1].len = 2;
+ Â Â Â Âarm_insn_r->arm_mems[1].addr = tgt_mem_addr;
+ Â Â Â Â/* record Rn also as it changes. Â*/
+ Â Â Â Âarm_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*2);
+ Â Â Â Âarm_insn_r->arm_regs[0] = 1;
+ Â Â Â Âarm_insn_r->arm_regs[1] = bits (arm_insn_r->arm_insn, 16,
19);

+ Â Â Â}
+ Â Â/* DSP insns (e.g. LDRD) ÂTBD. Â*/
+ Â}
+ Âelse if ((1 == arm_insn_r->decode) && (0x12 == opcode1)
+ Â Â Â Â Â && SBO_SBZ (arm_insn_r->arm_insn, 9, 12, 1))
+ Â Â{
+ Â Â Â/* handle BX, branch and link/exchange. Â*/
+ Â Â Â/* branch is chosen by setting T bit of CSPR, bitp[0] of Rm. Â*/
+ Â Â Âarm_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*2);
+ Â Â Âarm_insn_r->arm_regs[0] = 1;
+ Â Â Âarm_insn_r->arm_regs[1] = ARM_PS_REGNUM;
+ Â Â}
+ Âelse if ((1 == arm_insn_r->decode) && (0x16 == opcode1)
+ Â Â Â Â Â && SBO_SBZ (arm_insn_r->arm_insn, 9, 4, 1)
+ Â Â Â Â Â && SBO_SBZ (arm_insn_r->arm_insn, 17, 4, 1))
+ Â Â{
+ Â Â Â/* count leading zeros: CLZ. Â*/
+ Â Â Âprintf("handling CLZ - count leading zero insn\n");
+ Â Â Âarm_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*2);
+ Â Â Âarm_insn_r->arm_regs[0] = 1;
+ Â Â Âarm_insn_r->arm_regs[1] = bits (arm_insn_r->arm_insn, 12, 15);
+ Â Â}
+ Âelse if ((!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
+ Â Â Â Â Â&& ((8 == arm_insn_r->opcode) || (10 == arm_insn_r->opcode))
+ Â Â Â Â Â&& (SBO_SBZ (arm_insn_r->arm_insn, 17, 4, 1))
+ Â Â Â Â Â&& (SBO_SBZ (arm_insn_r->arm_insn, 1, 12, 0))
+ Â Â Â Â Â)
+ Â Â{
+ Â Â Â/* handle MRS insn. Â*/
+ Â Â Âarm_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*2);
+ Â Â Âarm_insn_r->arm_regs[0] = 1;
+ Â Â Âarm_insn_r->arm_regs[1] = bits (arm_insn_r->arm_insn, 12, 15);
+ Â Â}
+ Â/* following is always true, in case none of the above conditions meet, it
will fall here. Â*/
+ Âelse if (arm_insn_r->opcode <= 15)
+ Â Â{
+ Â Â Â/* normal data processing insns. Â*/
+ Â Â Â/* out of 11 shifter operands mode, all the insn modifies destination
+ Â Â Â Â Â Â Â Âregister, which is specified by 13-16 decode. Â*/
+ Â Â Âarm_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*3);
+ Â Â Âarm_insn_r->arm_regs[0] = 2;
+ Â Â Âarm_insn_r->arm_regs[1] = bits (arm_insn_r->arm_insn, 12, 15);
+ Â Â Âarm_insn_r->arm_regs[2] = ARM_PS_REGNUM;
+ Â Â}
+ Âreturn 0;
+}
+
+static int
+arm_handle_data_proc_imm_insn (void *data)
+{
+ Âinsn_decode_record *arm_insn_r = (insn_decode_record*) data;
+ Âstruct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch);
+ Âstruct regcache *reg_cache = Âarm_insn_r->regcache;
+
+ Âuint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
+ Âuint32_t immed_high = 0, immed_low = 0, offset_8 = 0, tgt_mem_addr = 0;
+
+ Âarm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
+ Âarm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
+
+ Âif (((9 == arm_insn_r->opcode) || (11 == arm_insn_r->opcode))
+ Â Â Â && (2 == bits (arm_insn_r->arm_insn, 20, 21))
+ Â Â Â && (SBO_SBZ (arm_insn_r->arm_insn, 13, 4, 1))
+ Â Â Â )
+ Â Â{
+ Â Â Â/* handle MSR insn. Â*/
+ Â Â Âarm_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*2);
+ Â Â Âif (9 == arm_insn_r->opcode)
+ Â Â Â {
+ Â Â Â Â /*CSPR is going to be changed. Â*/
+ Â Â Â Â arm_insn_r->arm_regs[0] = 1;
+ Â Â Â Â arm_insn_r->arm_regs[1] = ARM_PS_REGNUM;
+ Â Â Â }
+ Â Â Âelse
+ Â Â Â{
+ Â Â Â /* SPSR is going to be changed. Â*/
+ Â Â Â /* Oza: FIX ME ? how to read SPSR value? Â*/
+ Â Â Â}
+ Â Â}
+ Â/* following is always true, in case none of the above conditions meet, it
will fall

+ Â Â Â Âhere. Â*/
+ Âelse if (arm_insn_r->opcode <= 15)
+ Â Â{
+ Â Â Â/* normal data processing insns. Â*/
+ Â Â Â/* out of 11 shifter operands mode, all the insn modifies destination
+ Â Â Â Â Â Â Â Âregister, which is specified by 13-16 decode. Â*/
+ Â Â Âarm_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*3);
+ Â Â Âarm_insn_r->arm_regs[0] = 2;
+ Â Â Âarm_insn_r->arm_regs[1] = bits (arm_insn_r->arm_insn, 12, 15);
+ Â Â Âarm_insn_r->arm_regs[2] = ARM_PS_REGNUM;
+ Â Â}
+ Âreturn 0;
+}
+
+static int
+arm_handle_ld_st_imm_offset_insn (void *data)
+{
+ Âinsn_decode_record *arm_insn_r = (insn_decode_record*) data;
+ Âstruct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch);
+ Âstruct regcache *reg_cache = arm_insn_r->regcache;
+
+ Âuint32_t reg_src1 = 0 , reg_src2= 0, reg_dest = 0;
+ Âuint32_t immed_high = 0, immed_low = 0, offset_12 = 0, tgt_mem_addr = 0;
+
+ Âunion
+ Â Â{
+ Â Â Âuint32_t s_word;
+ Â Â Âgdb_byte buf[4];
+ Â Â} u_buf;
+
+ Âmemset(&u_buf, 0, sizeof(u_buf));
+ Âarm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
+ Âarm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
+
+ Âif (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
+ Â Â{
+ Â Â Âreg_dest = bits (arm_insn_r->arm_insn, 12, 15);
+ Â Â Â/* LDR insn has a capability to do branching, if
+ Â Â Â Â Â Â ÂMOV LR, PC is precedded by LDR insn having Rn as R15
+ Â Â Â Â Â Â Âin that case, it emulates branch and link insn, and hence we
+ Â Â Â Â Â Â Âneed to save CSPR and PC as well. Â*/
+ Â Â Âif (15 != reg_dest)
+ Â Â Â Â{
+ Â Â Â Â Âarm_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*2);
+ Â Â Â Â Âarm_insn_r->arm_regs[0] = 1;
+ Â Â Â Â Âarm_insn_r->arm_regs[1] = bits (arm_insn_r->arm_insn, 12, 15);
+ Â Â Â Â}
+ Â Â Âelse
+ Â Â Â Â{
+ Â Â Â Â Âarm_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*3);
+ Â Â Â Â Âarm_insn_r->arm_regs[0] = 2;
+ Â Â Â Â Âarm_insn_r->arm_regs[1] = reg_dest;
+ Â Â Â Â Âarm_insn_r->arm_regs[2] = ARM_PS_REGNUM;
+ Â Â Â Â}
+ Â Â}
+ Âelse
+ Â Â{
+ Â Â Âif ((8 == arm_insn_r->opcode) || (10 == arm_insn_r->opcode)
+ Â Â Â|| (12 == arm_insn_r->opcode) || (14 == arm_insn_r->opcode)
+ Â Â Â|| (9 == arm_insn_r->opcode) || (11 == arm_insn_r->opcode)
+ Â Â Â|| (13 == arm_insn_r->opcode) || (15 == arm_insn_r->opcode)
+ Â Â Â|| (0 == arm_insn_r->opcode) || (2 == arm_insn_r->opcode)
+ Â Â Â|| (4 == arm_insn_r->opcode) || (6 == arm_insn_r->opcode)
+ Â Â Â|| (1 == arm_insn_r->opcode) || (3 == arm_insn_r->opcode)
+ Â Â Â|| (5 == arm_insn_r->opcode) || (7 == arm_insn_r->opcode))
+ Â Â Â Â{
+ Â Â Â Â Â/* store, immediate offset, immediate pre-indexed,
+ Â Â Â Â Â Â Â Â Â Â Âimmediate post-indexed. Â*/
+ Â Â Â Â Âreg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
+ Â Â Â Â Âoffset_12 = bits (arm_insn_r->arm_insn, 0, 11);
+ Â Â Â Â ÂGET_REG_VAL (reg_cache, reg_src1, &u_buf.buf[0]);
+ Â Â Â Â Â/* U == 1 */
+ Â Â Â Â Âif (bit (arm_insn_r->arm_insn, 23))
+ Â Â Â Â Â Â{
+ Â Â Â Â Â Â Âtgt_mem_addr = u_buf.s_word + offset_12;
+ Â Â Â Â Â Â}
+ Â Â Â Â Âelse
+ Â Â Â Â Â Â{
+ Â Â Â Â Â Â tgt_mem_addr = u_buf.s_word - offset_12;
+ Â Â Â Â Â Â}
+
+ Â Â Â Â Âarm_insn_r->arm_mems = (struct arm_mem_r *)xmalloc (sizeof(struct
+ Â Â Â Â Âarm_mem_r)*2);
+ Â Â Â Â Âarm_insn_r->arm_mems[0].len = 1;
+
+ Â Â Â Â Âswitch(arm_insn_r->opcode)
+ Â Â Â Â Â Â{
+ Â Â Â Â Â Â Âcase 8:
+ Â Â Â Â Â Â Âcase 12:
+ Â Â Â Â Â Â Âcase 9:
+ Â Â Â Â Â Â Âcase 13:
+ Â Â Â Â Â Â Âcase 1:
+ Â Â Â Â Â Â Âcase 5:
+ Â Â Â Â Â Â Â Â/* STR insn, STRT insn. Â*/
+ Â Â Â Â Â Â Â Âarm_insn_r->arm_mems[1].len = 4;
+ Â Â Â Â Â Â Âbreak;
+
+ Â Â Â Â Â Â Âcase 10:
+ Â Â Â Â Â Â Âcase 14:
+ Â Â Â Â Â Â Âcase 11:
+ Â Â Â Â Â Â Âcase 15:
+ Â Â Â Â Â Â Âcase 3:
+ Â Â Â Â Â Â Âcase 7:
+ Â Â Â Â Â Â Â Â/* STRB insn, STRBT insn. Â*/
+ Â Â Â Â Â Â Â Âarm_insn_r->arm_mems[1].len = 1;
+ Â Â Â Â Â Â Âbreak;
+
+ Â Â Â Â Â Â Âdefault:
+ Â Â Â Â Â Â Â Â/* rest of the insns are unreachable for this addressing mode.
*/
+ Â Â Â Â Â Â Âbreak;
+ Â Â Â Â Â Â}
+ Â Â Â Â Âarm_insn_r->arm_mems[1].addr = tgt_mem_addr;
+ Â Â Â Â Âif ((9 == arm_insn_r->opcode) || (11 == arm_insn_r->opcode)
+ Â Â Â Â Â|| (13 == arm_insn_r->opcode) || (15 == arm_insn_r->opcode)
+ Â Â Â Â Â|| (0 == arm_insn_r->opcode) || (2 == arm_insn_r->opcode)
+ Â Â Â Â Â|| (4 == arm_insn_r->opcode) || (6 == arm_insn_r->opcode)
+ Â Â Â Â Â|| (1 == arm_insn_r->opcode) || (3 == arm_insn_r->opcode)
+ Â Â Â Â Â|| (5 == arm_insn_r->opcode) || (7 == arm_insn_r->opcode))
+ Â Â Â Â Â Â{
+ Â Â Â Â Â Â Â/* we are handling pre-indexed mode; post-indexed mode;
+ Â Â Â Â Â Â Â Â Â Â Â Â Â Â where Rn is going to be changed. Â*/
+ Â Â Â Â Â Â Âarm_insn_r->arm_regs = (uint32_t*)xmalloc
(sizeof(uint32_t)*2);

+ Â Â Â Â Â Â Âarm_insn_r->arm_regs[0] = 1;
+ Â Â Â Â Â Â Âarm_insn_r->arm_regs[1] = reg_src1;
+ Â Â Â Â Â Â}
+ Â Â Â Â}
+ Â Â}
+ Âreturn 0;
+}
+
+static int
+arm_handle_ld_st_reg_offset_insn (void *data)
+{
+ Âinsn_decode_record *arm_insn_r = (insn_decode_record*) data;
+ Âstruct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch);
+ Âstruct regcache *reg_cache = Âarm_insn_r->regcache;
+
+ Âuint32_t shift_imm = 0;
+ Âuint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
+ Âuint32_t immed_high = 0, immed_low = 0, offset_12 = 0, tgt_mem_addr = 0;
+
+ Âunion
+ Â Â{
+ Â Â Âint32_t signed_word;
+ Â Â Âuint32_t s_word;
+ Â Â Âgdb_byte buf[4];
+ Â Â} u_buf[2];
+
+ Âmemset(&u_buf, 0, sizeof(u_buf));
+ Âarm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
+ Âarm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
+
+ Â/* handle enhanced store insns and LDRD DSP insn,
+ Â Â Â Âlet us begin according to addressing modes for store insns
+ Â Â Â ÂSTRH insn. Â*/
+
+ Â/* LDR or STR? Â*/
+ Âif (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
+ Â Â{
+ Â Â Âreg_dest = bits (arm_insn_r->arm_insn, 12, 15);
+ Â Â Â/* LDR insn has a capability to do branching, if
+ Â Â Â Â Â Â ÂMOV LR, PC is precedded by LDR insn having Rn as R15
+ Â Â Â Â Â Â Âin that case, it emulates branch and link insn, and hence we
+ Â Â Â Â Â Â Âneed to save CSPR and PC as well. Â*/
+ Â Â Âif (15 != reg_dest)
+ Â Â Â Â{
+ Â Â Â Â Âarm_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*2);
+ Â Â Â Â Âarm_insn_r->arm_regs[0] = 1;
+ Â Â Â Â Âarm_insn_r->arm_regs[1] = bits (arm_insn_r->arm_insn, 12, 15);
+ Â Â Â Â}
+ Â Â Âelse
+ Â Â Â Â{
+ Â Â Â Â Âarm_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*3);
+ Â Â Â Â Âarm_insn_r->arm_regs[0] = 2;
+ Â Â Â Â Âarm_insn_r->arm_regs[1] = reg_dest;
+ Â Â Â Â Âarm_insn_r->arm_regs[2] = ARM_PS_REGNUM;
+ Â Â Â Â}
+ Â Â}
+ Âelse
+ Â Â{
+ Â Âif ((8 == arm_insn_r->opcode) || (10 == arm_insn_r->opcode)
+ Â Â|| (12 == arm_insn_r->opcode) || (14 == arm_insn_r->opcode)
+ Â Â|| (9 == arm_insn_r->opcode) || (11 == arm_insn_r->opcode)
+ Â Â|| (13 == arm_insn_r->opcode) || (15 == arm_insn_r->opcode)
+ Â Â|| (0 == arm_insn_r->opcode) || (2 == arm_insn_r->opcode)
+ Â Â|| (4 == arm_insn_r->opcode) || (6 == arm_insn_r->opcode)
+ Â Â|| (1 == arm_insn_r->opcode) || (3 == arm_insn_r->opcode)
+ Â Â|| (5 == arm_insn_r->opcode) || (7 == arm_insn_r->opcode))
+ Â Â Â{
+ Â Â Â Âif (! bits (arm_insn_r->arm_insn, 4, 11))
+ Â Â Â Â Â{
+ Â Â Â Â Â Â/* store insn, register offset and register pre-indexed,
+ Â Â Â Â Â Â Â Â Â Â Â Â Âregister post-indexed. Â*/
+ Â Â Â Â Â Â/* get Rm. Â*/
+ Â Â Â Â Â Âreg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
+ Â Â Â Â Â Â/* get Rn. Â*/
+ Â Â Â Â Â Âreg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
+ Â Â Â Â Â ÂGET_REG_VAL (reg_cache, reg_src1, &u_buf[0].buf[0]);
+ Â Â Â Â Â ÂGET_REG_VAL (reg_cache, reg_src2,
&u_buf[1].buf[0]);

+ Â Â Â Â Â Âif (15 == reg_src2)
+ Â Â Â Â Â Â Â{
+ Â Â Â Â Â Â Â Â/* if R15 was used as Rn, hence current PC+8. Â*/
+ Â Â Â Â Â Â Â Â/* pre-indexed mode doesnt reach here ; illegal insn. Â*/
+ Â Â Â Â Â Â Â Âu_buf[0].s_word = u_buf[0].s_word + 8;
+ Â Â Â Â Â Â Â}
+ Â Â Â Â Â Â/* calculate target store address, Rn +/- Rm, register offset. Â*/
+ Â Â Â Â Â Â/* U == 1. Â*/
+ Â Â Â Â Â Âif (bit (arm_insn_r->arm_insn, 23))
+ Â Â Â Â Â Â Â{
+ Â Â Â Â Â Â Â Âtgt_mem_addr = u_buf[0].s_word + u_buf[1].s_word;
+ Â Â Â Â Â Â Â}
+ Â Â Â Â Â Âelse
+ Â Â Â Â Â Â Â{
+ Â Â Â Â Â Â Â Âtgt_mem_addr = u_buf[1].s_word - u_buf[0].s_word;
+ Â Â Â Â Â Â Â}
+ Â Â Â Â Â Âarm_insn_r->arm_mems = (struct arm_mem_r *)xmalloc (sizeof(struct
+ Â Â Â Â Â Âarm_mem_r)*2);
+ Â Â Â Â Â Âarm_insn_r->arm_mems[0].len = 1;
+ Â Â Â Â Â Âswitch(arm_insn_r->opcode)
+ Â Â Â Â Â Â Â{
+ Â Â Â Â Â Â Â Âcase 8:
+ Â Â Â Â Â Â Â Âcase 12:
+ Â Â Â Â Â Â Â Âcase 9:
+ Â Â Â Â Â Â Â Âcase 13:
+ Â Â Â Â Â Â Â Âcase 1:
+ Â Â Â Â Â Â Â Âcase 5:
+ Â Â Â Â Â Â Â Â Â/* STR insn, STRT insn. Â*/
+ Â Â Â Â Â Â Â Â Âarm_insn_r->arm_mems[1].len = 4;
+ Â Â Â Â Â Â Â Âbreak;
+
+ Â Â Â Â Â Â Â Âcase 10:
+ Â Â Â Â Â Â Â Âcase 14:
+ Â Â Â Â Â Â Â Âcase 11:
+ Â Â Â Â Â Â Â Âcase 15:
+ Â Â Â Â Â Â Â Âcase 3:
+ Â Â Â Â Â Â Â Âcase 7:
+ Â Â Â Â Â Â Â Â Â/* STRB insn, STRBT insn. Â*/
+ Â Â Â Â Â Â Â Â Âarm_insn_r->arm_mems[1].len = 1;
+ Â Â Â Â Â Â Â Âbreak;
+
+ Â Â Â Â Â Â Â Âdefault:
+ Â Â Â Â Â Â Â Â Â/* rest of the insns are unreachable for this addr mode. Â*/
+ Â Â Â Â Â Â Â Âbreak;
+ Â Â Â Â Â Â Â}
+ Â Â Â Â Â Âarm_insn_r->arm_mems[1].addr = tgt_mem_addr;
+
+ Â Â Â Â Â Âif ((9 == arm_insn_r->opcode) || (11 == arm_insn_r->opcode)
+ Â Â Â Â Â Â|| (13 == arm_insn_r->opcode) || (15 == arm_insn_r->opcode)
+ Â Â Â Â Â Â|| (0 == arm_insn_r->opcode) || (2 == arm_insn_r->opcode)
+ Â Â Â Â Â Â|| (4 == arm_insn_r->opcode) || (6 == arm_insn_r->opcode)
+ Â Â Â Â Â Â|| (1 == arm_insn_r->opcode) || (3 == arm_insn_r->opcode)
+ Â Â Â Â Â Â|| (5 == arm_insn_r->opcode) || (7 == arm_insn_r->opcode))
+ Â Â Â Â Â Â Â{
+ Â Â Â Â Â Â Â Âarm_insn_r->arm_regs = \
+ Â Â Â Â Â Â Â Â(uint32_t*)xmalloc (sizeof(uint32_t)*2);
+ Â Â Â Â Â Â Â Âarm_insn_r->arm_regs[0] = 1;
+ Â Â Â Â Â Â Â Â/* Rn is going to be changed in pre-indexed mode and
+ Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Âpost-indexed mode as well. Â*/
+ Â Â Â Â Â Â Â Âarm_insn_r->arm_regs[1] = reg_src2;
+ Â Â Â Â Â Â Â}
+ Â Â Â Â Â}
+ Â Â Â Âelse
+ Â Â Â Â Â{
+ Â Â Â Â Â Â/* store insn, scaled register offset; scaled pre-indexed. Â*/
+ Â Â Â Â Â Âoffset_12 = bits (arm_insn_r->arm_insn, 5, 6);
+ Â Â Â Â Â Â/* get Rm. Â*/
+ Â Â Â Â Â Âreg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
+ Â Â Â Â Â Â/* get Rn. Â*/
+ Â Â Â Â Â Âreg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
+ Â Â Â Â Â Â/* get shift_imm. Â*/
+ Â Â Â Â Â Âshift_imm = bits (arm_insn_r->arm_insn, 7, 11);
+ Â Â Â Â Â ÂGET_REG_VAL (reg_cache, reg_src1, &u_buf[0].buf[0]);
+ Â Â Â Â Â ÂGET_REG_VAL (reg_cache, reg_src2, &u_buf[1].buf[0]);
+ Â Â Â Â Â Â/* offset_12 used as shift. Â*/
+ Â Â Â Â Â Âswitch(offset_12)
+ Â Â Â Â Â Â Â{
+ Â Â Â Â Â Â Â Âcase 0:
+ Â Â Â Â Â Â Â Â Â/* offset_12 used as index. Â*/
+ Â Â Â Â Â Â Â Â Âoffset_12 = u_buf[0].s_word << shift_imm;
+ Â Â Â Â Â Â Â Âbreak;
+
+ Â Â Â Â Â Â Â Âcase 1:
+ Â Â Â Â Â Â Â Â Âoffset_12 = (!shift_imm)?0:u_buf[0].s_word >> shift_imm;
+ Â Â Â Â Â Â Â Âbreak;
+
+ Â Â Â Â Â Â Â Âcase 2:
+ Â Â Â Â Â Â Â Â Âif (!shift_imm)
+ Â Â Â Â Â Â Â Â Â Â{
+ Â Â Â Â Â Â Â Â Â Â Âif (bit (u_buf[0].s_word, 31))
+ Â Â Â Â Â Â Â Â Â Â Â Â{
+ Â Â Â Â Â Â Â Â Â Â Â Â Âoffset_12 = 0xFFFFFFFF;
+ Â Â Â Â Â Â Â Â Â Â Â Â}
+ Â Â Â Â Â Â Â Â Â Â Âelse
+ Â Â Â Â Â Â Â Â Â Â Â Â{
+ Â Â Â Â Â Â Â Â Â Â Â Â Âoffset_12 = 0;
+ Â Â Â Â Â Â Â Â Â Â Â Â}
+ Â Â Â Â Â Â Â Â Â Â}
+ Â Â Â Â Â Â Â Â Âelse
+ Â Â Â Â Â Â Â Â Â Â{
+ Â Â Â Â Â Â Â Â Â Â Â/* this is arithmetic shift. Â*/
+ Â Â Â Â Â Â Â Â Â Â Âoffset_12 = u_buf[0].signed_word >> shift_imm;
+ Â Â Â Â Â Â Â Â Â Â}
+ Â Â Â Â Â Â Â Â Âbreak;
+
+ Â Â Â Â Â Â Â Âcase 3:
+ Â Â Â Â Â Â Â Â Âif (!shift_imm)
+ Â Â Â Â Â Â Â Â Â Â{
+ Â Â Â Â Â Â Â Â Â Â ÂGET_REG_VAL (reg_cache, ARM_PS_REGNUM, &u_buf[1].buf[0]);
+ Â Â Â Â Â Â Â Â Â Â Â/* get C flag value and shift it by 31. Â*/
+ Â Â Â Â Â Â Â Â Â Â Âoffset_12 = (((bit (u_buf[1].s_word, 29)) << 31) \
+ Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â| (u_buf[0].s_word) >> 1);
+ Â Â Â Â Â Â Â Â Â Â}
+ Â Â Â Â Â Â Â Â Âelse
+ Â Â Â Â Â Â Â Â Â Â{
+ Â Â Â Â Â Â Â Â Â Â Âoffset_12 = (u_buf[0].s_word >> shift_imm) \
+ Â Â Â Â Â Â Â Â Â Â Â Â Â Â| (u_buf[0].s_word <<
(sizeof(uint32_t)-shift_imm));
+ Â Â Â Â Â Â Â Â Â Â}
+ Â Â Â Â Â Â Â Âbreak;
+
+ Â Â Â Â Â Â Â Âdefault:
+ Â Â Â Â Â Â Â Â Â/* unreachable. Â*/
+ Â Â Â Â Â Â Â Âbreak;
+ Â Â Â Â Â Â Â}
+
+ Â Â Â Â Â ÂGET_REG_VAL (reg_cache, reg_src2, &u_buf[1].buf[0]);
+ Â Â Â Â Â Â/* U == 1 */
+ Â Â Â Â Â Âif (bit (arm_insn_r->arm_insn, 23))
+ Â Â Â Â Â Â Â{
+ Â Â Â Â Â Â Â Âtgt_mem_addr = u_buf[1].s_word + offset_12;
+ Â Â Â Â Â Â Â}
+ Â Â Â Â Â Âelse
+ Â Â Â Â Â Â Â{
+ Â Â Â Â Â Â Â Âtgt_mem_addr = u_buf[1].s_word - offset_12;
+ Â Â Â Â Â Â Â}
+
+ Â Â Â Â Â Âarm_insn_r->arm_mems = (struct arm_mem_r *)
+ Â Â Â Â Â Â Â Â Â Â Â Âxmalloc (sizeof(struct arm_mem_r)*2);
+ Â Â Â Â Â Âarm_insn_r->arm_mems[0].len = 1;
+ Â Â Â Â Â Âarm_insn_r->arm_mems[1].addr = tgt_mem_addr;
+ Â Â Â Â Â Âswitch (arm_insn_r->opcode)
+ Â Â Â Â Â Â Â{
+ Â Â Â Â Â Â Â Âcase 8:
+ Â Â Â Â Â Â Â Âcase 12:
+ Â Â Â Â Â Â Â Âcase 9:
+ Â Â Â Â Â Â Â Âcase 13:
+ Â Â Â Â Â Â Â Âcase 1:
+ Â Â Â Â Â Â Â Âcase 5:
+ Â Â Â Â Â Â Â Â Â/* STR insn, STRT insn. Â*/
+ Â Â Â Â Â Â Â Â Âarm_insn_r->arm_mems[1].len = 4;
+ Â Â Â Â Â Â Â Âbreak;
+
+ Â Â Â Â Â Â Â Âcase 10:
+ Â Â Â Â Â Â Â Âcase 14:
+ Â Â Â Â Â Â Â Âcase 11:
+ Â Â Â Â Â Â Â Âcase 15:
+ Â Â Â Â Â Â Â Âcase 3:
+ Â Â Â Â Â Â Â Âcase 7:
+ Â Â Â Â Â Â Â Â Â/* STRB insn, STRBT insn. Â*/
+ Â Â Â Â Â Â Â Â Âarm_insn_r->arm_mems[1].len = 1;
+ Â Â Â Â Â Â Â Âbreak;
+
+ Â Â Â Â Â Â Â Âdefault:
+ Â Â Â Â Â Â Â Â Â/* rest of the insns are unreachable for this addr mode. Â*/
+ Â Â Â Â Â Â Â Âbreak;
+ Â Â Â Â Â Â Â}
+ Â Â Â Â Â Âif ((9 == arm_insn_r->opcode) || (11 == arm_insn_r->opcode)
+ Â Â Â Â Â Â|| (13 == arm_insn_r->opcode) || (15 == arm_insn_r->opcode)
+ Â Â Â Â Â Â|| (0 == arm_insn_r->opcode) || (2 == arm_insn_r->opcode)
+ Â Â Â Â Â Â|| (4 == arm_insn_r->opcode) || (6 == arm_insn_r->opcode)
+ Â Â Â Â Â Â|| (1 == arm_insn_r->opcode) || (3 == arm_insn_r->opcode)
+ Â Â Â Â Â Â|| (5 == arm_insn_r->opcode) || (7 == arm_insn_r->opcode))
+ Â Â Â Â Â Â Â{
+ Â Â Â Â Â Â Â Âarm_insn_r->arm_regs = \
+ Â Â Â Â Â Â Â Â(uint32_t*)xmalloc (sizeof(uint32_t)*2);
+ Â Â Â Â Â Â Â Âarm_insn_r->arm_regs[0] = 1;
+ Â Â Â Â Â Â Â Â/* Rn is going to be changed in register scaled pre-indexed
+ Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Âmode, and scaled post indexed mode. Â*/
+ Â Â Â Â Â Â Â Âarm_insn_r->arm_regs[1] = reg_src2;
+ Â Â Â Â Â Â Â}
+ Â Â Â Â Â}
+ Â Â Â}
+ Â Â}
+ Âreturn 0;
+}
+
+static int
+arm_hamdle_ld_st_multiple_insn (void *data)
+{
+ Âinsn_decode_record *arm_insn_r = (insn_decode_record*) data;
+ Âstruct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch);
+ Âstruct regcache *reg_cache = Âarm_insn_r->regcache;
+
+ Âuint32_t register_list[16]={0}, register_count=0, register_bits=0;
+ Âuint32_t shift_imm=0;
+ Âuint32_t reg_src1=0, reg_src2=0, addr_mode=0;
+ Âuint32_t start_address=0, index = 0;
+
+ Âunion
+ Â Â{
+ Â Â Âuint32_t s_word;
+ Â Â Âgdb_byte buf[4];
+ Â Â} u_buf[2];
+
+ Âmemset (&u_buf, 0, sizeof(u_buf));
+
+ Â/* this mode is exclusively for load and store multiple. Â*/
+ Â/* handle incremenrt after/before and decrment after.before mode;
+ Â Â Â ÂRn is chaging depending on W bit, but as of now we store Rn too wihtout
going for

+ Â Â Â Âoptmization. Â*/
+
+
+ Âif (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
+ Â Â{
+ Â Â Â/* LDR (1,2,3) where LDR (3) changes CPSR too. Â*/
+
+ Â Â Âregister_bits = bits (arm_insn_r->arm_insn, 0, 15);
+ Â Â Â/* get Rn. Â*/
+ Â Â Âreg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
+ Â Â Âwhile (register_bits)
+ Â Â Â {
+ Â Â Â Â if (register_bits & 0x00000001)
+ Â Â Â Â Â register_list[register_count++] = 1;
+ Â Â Â Â register_bits = register_bits >> 1;
+ Â Â Â }
+
+ Â Â Â Â/* extra space for Base Register and CPSR; wihtout optmization. Â*/
+ Â Â Â Âarm_insn_r->arm_regs = (uint32_t*)xmalloc \
+ Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â(sizeof(uint32_t) * (register_count +
3));
+ Â Â Â Âarm_insn_r->arm_regs[0] = register_count + 2;
+ Â Â Â Âarm_insn_r->arm_regs[register_count+1] = reg_src1;
+ Â Â Â Âarm_insn_r->arm_regs[register_count+2] = ARM_PS_REGNUM;
+ Â Â Â Âfor (register_count = 0; register_count < 8; register_count++)
+ Â Â Â Â Â{
+ Â Â Â Â Â Âif Â(register_list[register_count])
+ Â Â Â Â Â Â Â{
+ Â Â Â Â Â Â Â Âarm_insn_r->arm_regs[index] = register_count;
+ Â Â Â Â Â Â Â Âindex++;
+ Â Â Â Â Â Â Â}
+ Â Â Â Â Â}
+ Â Â}
+ Âelse
+ Â Â{
+ Â Â/* it handles both STM(1) and STM(2). Â*/
+ Â Âaddr_mode = bits (arm_insn_r->arm_insn, 23, 24);
+
+ Â Âregister_bits = bits (arm_insn_r->arm_insn, 0, 15);
+ Â Â/* get Rn. Â*/
+ Â Âreg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
+ Â ÂGET_REG_VAL (reg_cache, reg_src1, &u_buf[0].buf[0]);
+ Â Âwhile (register_bits)
+ Â Â Â{
+ Â Â Â Âif (register_bits & 0x00000001)
+ Â Â Â Â Â register_count++;
+ Â Â Â Âregister_bits = register_bits >> 1;
+ Â Â Â}
+
+ Â Âswitch(addr_mode)
+ Â Â Â{
+ Â Â Â Â/* Decrement after. Â*/
+ Â Â Â Âcase 0:
+ Â Â Â Â Âstart_address = (u_buf[0].s_word) - (register_count * 4) + 4;
+ Â Â Â Â Âarm_insn_r->arm_mems = (struct arm_mem_r *)xmalloc (sizeof(struct
+ Â Â Â Â Âarm_mem_r)*(register_count+1));
+ Â Â Â Â Âarm_insn_r->arm_mems[0].len = register_count;
+ Â Â Â Â Âwhile (register_count)
+ Â Â Â Â Â Â{
+ Â Â Â Â Â Â Âarm_insn_r->arm_mems[register_count].addr = start_address;
+ Â Â Â Â Â Â Âarm_insn_r->arm_mems[register_count].len = 4;
+ Â Â Â Â Â Â Âstart_address = start_address + 4;
+ Â Â Â Â Â Â Âregister_count--;
+ Â Â Â Â Â Â}
+ Â Â Â Âbreak;
+
+ Â Â Â Â/* Increment after. Â*/
+ Â Â Â Âcase 1:
+ Â Â Â Â Âstart_address = u_buf[0].s_word;
+ Â Â Â Â Âarm_insn_r->arm_mems = (struct arm_mem_r *)xmalloc (sizeof(struct
+ Â Â Â Â Âarm_mem_r)*(register_count+1));
+ Â Â Â Â Âarm_insn_r->arm_mems[0].len = register_count;
+ Â Â Â Â Âwhile (register_count)
+ Â Â Â Â Â Â{
+ Â Â Â Â Â Â Âarm_insn_r->arm_mems[register_count].addr = start_address;
+ Â Â Â Â Â Â Âarm_insn_r->arm_mems[register_count].len = 4;
+ Â Â Â Â Â Â Âstart_address = start_address + 4;
+ Â Â Â Â Â Â Âregister_count--;
+ Â Â Â Â Â Â}
+ Â Â Â Âbreak;
+
+ Â Â Â Â/* Decrement before. Â*/
+ Â Â Â Âcase 2:
+
+ Â Â Â Â Âstart_address = (u_buf[0].s_word) - (register_count * 4);
+ Â Â Â Â Âarm_insn_r->arm_mems = (struct arm_mem_r *)xmalloc (sizeof(struct
+ Â Â Â Â Âarm_mem_r)*(register_count+1));
+ Â Â Â Â Âarm_insn_r->arm_mems[0].len = register_count;
+ Â Â Â Â Âwhile (register_count)
+ Â Â Â Â Â Â{
+ Â Â Â Â Â Â Âarm_insn_r->arm_mems[register_count].addr = start_address;
+ Â Â Â Â Â Â Âarm_insn_r->arm_mems[register_count].len = 4;
+ Â Â Â Â Â Â Âstart_address = start_address + 4;
+ Â Â Â Â Â Â Âregister_count--;
+ Â Â Â Â Â Â}
+ Â Â Â Âbreak;
+
+ Â Â Â Â/* Increment before. Â*/
+ Â Â Â Âcase 3:
+ Â Â Â Â Âstart_address = u_buf[0].s_word + 4;
+ Â Â Â Â Âarm_insn_r->arm_mems = (struct arm_mem_r *)xmalloc (sizeof(struct
+ Â Â Â Â Âarm_mem_r)*(register_count+1));
+ Â Â Â Â Âarm_insn_r->arm_mems[0].len = register_count;
+ Â Â Â Â Âwhile (register_count)
+ Â Â Â Â Â Â{
+ Â Â Â Â Â Â Âarm_insn_r->arm_mems[register_count].addr = start_address;
+ Â Â Â Â Â Â Âarm_insn_r->arm_mems[register_count].len = 4;
+ Â Â Â Â Â Â Âstart_address = start_address + 4;
+ Â Â Â Â Â Â Âregister_count--;
+ Â Â Â Â Â Â}
+ Â Â Â Âbreak;
+
+ Â Â Â Âdefault:
+ Â Â Â Â Â/* unreachable. Â*/
+ Â Â Â Âbreak;
+ Â Â Â}
+
+ Â Â/* base register also changes; based on condition and W bit. Â*/
+ Â Â/* we save it anyway without optimization. Â*/
+ Â Âarm_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*2);
+ Â Âarm_insn_r->arm_regs[0] = 1;
+ Â Âarm_insn_r->arm_regs[1] = reg_src1;
+ Â Â}
+ Âreturn 0;
+}
+
+static int
+arm_handle_brn_insn (void *data)
+{
+ Âinsn_decode_record *arm_insn_r = (insn_decode_record*) data;
+ Â/* handle B, BL, BLX(1) insns. Â*/
+ Â/* wihtout optmization we save link register,
+ Â Â Â ÂCSPR for the insn which changes T bit. Â*/
+ Âarm_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*3);
+ Âarm_insn_r->arm_regs[0] = 2;
+ Âarm_insn_r->arm_regs[1] = ARM_PS_REGNUM;
+ Âarm_insn_r->arm_regs[2] = ARM_LR_REGNUM;
+
+ Âreturn 0;
+}
+
+static int
+arm_handle_coproc_insn (void *data)
+{
+ Â return -1;
+}
+
+static int
+arm_handle_coproc_data_proc_insn (void *data)
+{
+
+ Â insn_decode_record *arm_insn_r = (insn_decode_record*) data;
+ Â struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch);
+ Â struct regcache *reg_cache = arm_insn_r->regcache;
+
+ Â uint32_t shift_imm = 0;
+ Â uint32_t reg_src1 = 0, reg_src2 = 0, addr_mode = 0;
+ Â uint32_t start_address = 0;
+
+ Â /* handle SWI insn; system call would be handled over here. Â*/
+
+ Â arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27);
+ Â if (15 == arm_insn_r->opcode)
+ Â {
+ Â Â Â Â/* handle arm syscall insn. Â*/
+ Â Â Â Âif (tdep->arm_swi_record != NULL)
+ Â Â Â Â Â{
+ Â Â Â Â Â Âtdep->arm_swi_record(reg_cache);
+ Â Â Â Â Â}
+ Â Â Â Âelse
+ Â Â Â Â Â{
+ Â Â Â Â Â Âreturn -1;
+ Â Â Â Â Â}
+ Â }
+
+ Â return -1;
+}
+
+
+static int
+thumb_handle_shift_add_sub_insn (void *data)
+{
+ Âinsn_decode_record *thumb_insn_r = (insn_decode_record*) data;
+ Âstruct gdbarch_tdep *tdep = gdbarch_tdep ( Âthumb_insn_r->gdbarch);
+ Âstruct regcache *reg_cache = Âthumb_insn_r->regcache;
+
+ Âuint32_t reg_src1 = 0;
+
+
+ Âunion
+ Â Â{
+ Â Â Âuint32_t s_word;
+ Â Â Âgdb_byte buf[4];
+ Â Â} u_buf;
+
+ Âreg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
+
+ Âthumb_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*3);
+ Âthumb_insn_r->arm_regs[0] = 2;
+ Âthumb_insn_r->arm_regs[1] = ARM_PS_REGNUM;
+ Âthumb_insn_r->arm_regs[2] = reg_src1;
+
+ Âreturn 0;
+}
+
+static int
+thumb_handle_add_sub_cmp_mov_insn (void *data)
+{
+ Âinsn_decode_record *thumb_insn_r = (insn_decode_record*) data;
+ Âstruct gdbarch_tdep *tdep = gdbarch_tdep (thumb_insn_r->gdbarch);
+ Âstruct regcache *reg_cache = thumb_insn_r->regcache;
+
+ Âuint32_t reg_src1 = 0;
+
+
+ Âunion
+ Â{
+ Â Âuint32_t s_word;
+ Â Âgdb_byte buf[4];
+ Â} u_buf;
+
+ Âreg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
+
+ Âthumb_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*3);
+ Âthumb_insn_r->arm_regs[0] = 2;
+ Âthumb_insn_r->arm_regs[1] = ARM_PS_REGNUM;
+ Âthumb_insn_r->arm_regs[2] = reg_src1;
+
+ Âreturn 0;
+}
+
+static int
+thumb_handle_ld_st_reg_offset_insn (void *data)
+{
+ Âinsn_decode_record *thumb_insn_r = (insn_decode_record*) data;
+ Âstruct gdbarch_tdep *tdep = gdbarch_tdep (thumb_insn_r->gdbarch);
+ Âstruct regcache *reg_cache = Âthumb_insn_r->regcache;
+
+ Âuint32_t reg_src1 = 0, reg_src2 = 0;
+ Âuint32_t opcode1 = 0, opcode2 = 0, opcode3 = 0;
+
+
+ Âunion
+ Â Â{
+ Â Â Âuint32_t s_word;
+ Â Â Âgdb_byte buf[4];
+ Â Â} u_buf[2];
+
+ Âif (bit (thumb_insn_r->arm_insn, 12))
+ Â Â{
+ Â Â Â/* handle load/store register offset. Â*/
+ Â Â Âopcode1 = bits (thumb_insn_r->arm_insn, 11, 12);
+ Â Â Âopcode2 = bits (thumb_insn_r->arm_insn, 9, 10);
+ Â Â Âif ((opcode2 >= 12) && (opcode2 <= 15))
+ Â Â Â Â{
+ Â Â Â Â Â/* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. Â*/
+ Â Â Â Â Âreg_src1 = bits (thumb_insn_r->arm_insn,0, 2);
+ Â Â Â Â Âthumb_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*2);
+ Â Â Â Â Âthumb_insn_r->arm_regs[0] = 1;
+ Â Â Â Â Âthumb_insn_r->arm_regs[1] = reg_src1;
+ Â Â Â Â}
+ Â Â Âelse if ((opcode2 >= 8) && (opcode2 <= 10))
+ Â Â Â Â{
+ Â Â Â Â Â/* STR(2), STRB(2), STRH(2) . Â*/
+ Â Â Â Â Âreg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
+ Â Â Â Â Âreg_src2 = bits (thumb_insn_r->arm_insn, 6, 8);
+ Â Â Â Â ÂGET_REG_VAL (reg_cache, reg_src1, &u_buf[0].buf[0]);
+ Â Â Â Â ÂGET_REG_VAL (reg_cache, reg_src2, &u_buf[1].buf[0]);
+ Â Â Â Â Âthumb_insn_r->arm_mems = (struct arm_mem_r *) Â\
+ Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Âxmalloc (sizeof(struct arm_mem_r) * 2);
+ Â Â Â Â Âthumb_insn_r->arm_mems[0].len = 1;
+ Â Â Â Â Âthumb_insn_r->arm_mems[0].addr = u_buf[0].s_word+u_buf[1].s_word;
+ Â Â Â Â Âif (8 == opcode2)
+ Â Â Â Â Â Âthumb_insn_r->arm_mems[0].len = 4; Â Â/* STR (2). Â*/
+ Â Â Â Â Âelse if (10 == opcode2)
+ Â Â Â Â Â Âthumb_insn_r->arm_mems[0].len = 1; Â Â/* ÂSTRB (2). Â*/
+ Â Â Â Â Âelse if (9 == opcode2)
+ Â Â Â Â Â Âthumb_insn_r->arm_mems[0].len = 2; Â Â/* STRH (2). Â*/
+ Â Â Â Â}
+ Â Â Âgoto end;
+ Â Â}
+ Âelse if (bit (thumb_insn_r->arm_insn, 11))
+ Â Â{
+ Â Â Â/* handle load from literal pool. Â*/
+ Â Â Â/* LDR(3). Â*/
+ Â Â Âreg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);

+ Â Â Âthumb_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*2);
+ Â Â Âthumb_insn_r->arm_regs[0] = 1;
+ Â Â Âthumb_insn_r->arm_regs[1] = reg_src1;
+ Â Â Âgoto end;
+ Â Â}
+
+ Âthumb_insn_r->opcode = bits (thumb_insn_r->arm_insn, 13, 15);
+ Âopcode1 = bits (thumb_insn_r->arm_insn, 10, 12);
+ Âif (opcode1)
+ Â Â{
+ Â Â Âopcode2 = bits (thumb_insn_r->arm_insn, 8, 9);
+ Â Â Âopcode3 = bits (thumb_insn_r->arm_insn, 0, 2);
+ Â Â Âif ((3 == opcode2) && (!opcode3))
+ Â Â Â Â{
+ Â Â Â Â Â/* branch with exchange. Â*/
+ Â Â Â Â Âthumb_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*2);
+ Â Â Â Â Âthumb_insn_r->arm_regs[0] = 1;
+ Â Â Â Â Âthumb_insn_r->arm_regs[1] = ARM_PS_REGNUM;
+ Â Â Â Â}
+ Â Â Âelse
+ Â Â Â Â{
+ Â Â Â Â Â/* format 8; special data processing insns. Â*/
+ Â Â Â Â Âreg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
+ Â Â Â Â Âthumb_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*3);
+ Â Â Â Â Âthumb_insn_r->arm_regs[0] = 2;
+ Â Â Â Â Âthumb_insn_r->arm_regs[1] = ARM_PS_REGNUM;
+ Â Â Â Â Âthumb_insn_r->arm_regs[2] = reg_src1;
+ Â Â Â Â}
+ Â Â}
+ Âelse
+ Â Â{
+ Â Â Â/* format 5; data processing insns. Â*/
+ Â Â Âreg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
+ Â Â Âif (bit (thumb_insn_r->arm_insn, 7))
+ Â Â Â Â{
+ Â Â Â Â Âreg_src1 = reg_src1 + 8;
+ Â Â Â Â}
+ Â Â Âthumb_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*3);
+ Â Â Âthumb_insn_r->arm_regs[0] = 2;
+ Â Â Âthumb_insn_r->arm_regs[1] = ARM_PS_REGNUM;
+ Â Â Âthumb_insn_r->arm_regs[2] = reg_src1;
+ Â Â}
+
+ Âend:
+ Âreturn 0;
+}
+
+static int
+thumb_handle_ld_st_imm_offset_insn (void *data)
+{
+ Âinsn_decode_record *thumb_insn_r = (insn_decode_record*) data;
+ Âstruct gdbarch_tdep *tdep = gdbarch_tdep (thumb_insn_r->gdbarch);
+ Âstruct regcache *reg_cache = (struct regcache*) thumb_insn_r->regcache;
+
+ Âuint32_t reg_val1 = 0;
+ Âuint32_t reg_src1 = 0;
+ Âuint32_t opcode = 0, immed_5 = 0;
+
+ Âunion
+ Â Â{
+ Â Â Âuint32_t s_word;
+ Â Â Âgdb_byte buf[4];
+ Â Â} u_buf;
+
+ Âopcode = bits (thumb_insn_r->arm_insn, 11, 12);
+
+ Âif (opcode)
+ Â Â{
+ Â Â Â/* LDR(1). Â*/
+ Â Â Âreg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
+ Â Â Âthumb_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*2);
+ Â Â Âthumb_insn_r->arm_regs[0] = 1;
+ Â Â Âthumb_insn_r->arm_regs[1] = reg_src1;
+ Â Â}
+ Âelse
+ Â Â{
+ Â Â Â/* STR(1). Â*/
+ Â Â Âreg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
+ Â Â Âimmed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
+ Â Â ÂGET_REG_VAL (reg_cache, reg_src1, &u_buf.buf[0]);
+ Â Â Âthumb_insn_r->arm_mems = (struct arm_mem_r *)xmalloc (sizeof(struct
+ Â Â Â Âarm_mem_r)*2);
+ Â Â Âthumb_insn_r->arm_mems[0].len = 1;
+ Â Â Âthumb_insn_r->arm_mems[1].len = 4;
+ Â Â Âthumb_insn_r->arm_mems[1].addr = u_buf.s_word + (immed_5 * 4);
+ Â Â}
+
+ Âreturn 0;
+}
+
+static int
+thumb_hamdle_ld_st_stack_insn (void *data)
+{
+ Âinsn_decode_record *thumb_insn_r = (insn_decode_record*) data;
+ Âstruct gdbarch_tdep *tdep = gdbarch_tdep (thumb_insn_r->gdbarch);
+ Âstruct regcache *reg_cache = (struct regcache*) thumb_insn_r->regcache;
+
+ Âuint32_t reg_val1 = 0;
+ Âuint32_t reg_src1 = 0;
+ Âuint32_t opcode = 0, immed_8 = 0, immed_5 = 0;
+
+ Âunion
+ Â Â{
+ Â Â Âuint32_t s_word;
+ Â Â Âgdb_byte buf[4];
+ Â Â} u_buf;
+
+ Âopcode = bits (thumb_insn_r->arm_insn, 11, 12);
+
+ Âif (3 == opcode)
+ Â Â{
+ Â Â Â/* LDR(4). Â*/
+ Â Â Âreg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
+ Â Â Âthumb_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*2);
+ Â Â Âthumb_insn_r->arm_regs[0] = 1;
+ Â Â Âthumb_insn_r->arm_regs[1] = reg_src1;
+ Â Â}
+ Âelse if (1 == opcode)
+ Â Â{
+ Â Â Â/* LDRH(1). Â*/
+ Â Â Âreg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
+ Â Â Âthumb_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*2);
+ Â Â Âthumb_insn_r->arm_regs[0] = 1;
+ Â Â Âthumb_insn_r->arm_regs[1] = reg_src1;
+ Â Â}
+ Âelse if (2 == opcode)
+ Â Â{
+ Â Â Â/* STR(3). Â*/
+ Â Â Âimmed_8 = bits (thumb_insn_r->arm_insn, 0, 7);
+ Â Â ÂGET_REG_VAL (reg_cache, ARM_SP_REGNUM, &u_buf.buf[0]);
+ Â Â Âthumb_insn_r->arm_mems = (struct arm_mem_r *)xmalloc (sizeof(struct
+ Â Â Â Âarm_mem_r)*2);
+ Â Â Âthumb_insn_r->arm_mems[0].len = 1;
+ Â Â Âthumb_insn_r->arm_mems[1].len = 4;
+ Â Â Âthumb_insn_r->arm_mems[1].addr = u_buf.s_word + (immed_8 * 4);
+ Â Â}
+ Âelse if (0 == opcode)
+ Â Â{
+ Â Â Â/* STRH(1). Â*/
+ Â Â Âimmed_5 = bits (thumb_insn_r->arm_insn, 6, 10);
+ Â Â Âreg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
+ Â Â ÂGET_REG_VAL (reg_cache, reg_src1, &u_buf.buf[0]);
+ Â Â Âthumb_insn_r->arm_mems = (struct arm_mem_r *)xmalloc (sizeof(struct
+ Â Â Â Âarm_mem_r)*2);
+ Â Â Âthumb_insn_r->arm_mems[0].len = 1;
+ Â Â Âthumb_insn_r->arm_mems[1].len = 2;
+ Â Â Âthumb_insn_r->arm_mems[1].addr = u_buf.s_word + (immed_5 * 2);
+ Â Â}
+ Âreturn 0;
+}
+
+static int
+thumb_handle_misc_insn (void *data)
+{
+ Âinsn_decode_record *thumb_insn_r = (insn_decode_record*) data;
+ Âstruct gdbarch_tdep *tdep = gdbarch_tdep (thumb_insn_r->gdbarch);
+ Âstruct regcache *reg_cache = (struct regcache*) thumb_insn_r->regcache;
+
+ Âuint32_t reg_val1 = 0;
+ Âuint32_t reg_src1 = 0;
+ Âuint32_t opcode = 0, opcode1 = 0, opcode2 = 0, immed_8 = 0, immed_5 = 0;
+ Âuint32_t register_bits = 0, register_count = 0;
+ Âuint32_t register_list[8] = {0}, index = 0, start_address = 0;
+
+ Âunion
+ Â Â{
+ Â Â Âuint32_t s_word;
+ Â Â Âgdb_byte buf[4];
+ Â Â} u_buf;
+
+ Âopcode = bits (thumb_insn_r->arm_insn, 11, 12);
+ Âopcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
+ Âopcode2 = bits (thumb_insn_r->arm_insn, 9, 12);
+
+ Âif (14 == opcode2)
+ Â Â{
+ Â Â Â/* POP. Â*/
+ Â Â Âregister_bits = bits (thumb_insn_r->arm_insn, 0, 7);
+ Â Â Âwhile (register_bits)
+ Â Â Â Â{
+ Â Â Â Â Âif (register_bits & 0x00000001)
+ Â Â Â Â Â Âregister_list[register_count++] = 1;
+ Â Â Â Â Âregister_bits = register_bits >> 1;
+ Â Â Â Â}
+ Â Â Â Âthumb_insn_r->arm_regs = (uint32_t*)xmalloc \
+ Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â(sizeof(uint32_t) * (register_count +
3));
+ Â Â Â Âthumb_insn_r->arm_regs[0] = register_count + 2;
+ Â Â Â Âthumb_insn_r->arm_regs[register_count + 1] = ARM_PS_REGNUM;
+ Â Â Â Âthumb_insn_r->arm_regs[register_count + 2] = ARM_SP_REGNUM;
+ Â Â Âfor (register_count = 0; register_count < 8; register_count++)
+ Â Â Â Â{
+ Â Â Â Â Âif Â(register_list[register_count])
+ Â Â Â Â Â Â{
+ Â Â Â Â Â Â Âthumb_insn_r->arm_regs[index] = register_count;
+ Â Â Â Â Â Â Âindex++;
+ Â Â Â Â Â Â}
+ Â Â Â Â}
+ Â Â}
+ Âelse if (10 == opcode2)
+ Â Â{
+ Â Â Â/* PUSH. Â*/
+ Â Â Âregister_bits = bits (thumb_insn_r->arm_insn, 0, 7);
+ Â Â ÂGET_REG_VAL (reg_cache, ARM_PC_REGNUM, &u_buf.buf[0]);
+ Â Â Âwhile (register_bits)
+ Â Â Â Â{
+ Â Â Â Â Âif (register_bits & 0x00000001)
+ Â Â Â Â Â Â register_count++;
+ Â Â Â Â Âregister_bits = register_bits >> 1;
+ Â Â Â Â}
+ Â Â Âstart_address = u_buf.s_word - Â\
+ Â Â Â Â Â Â Â Â Â (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count)) ;
+ Â Â Âthumb_insn_r->arm_mems = (struct arm_mem_r *)xmalloc (sizeof(struct
+ Â Â Âarm_mem_r)*(register_count + 1));
+ Â Â Âthumb_insn_r->arm_mems[0].len = register_count;
+ Â Â Âwhile (register_count)
+ Â Â Â Â{
+ Â Â Â Â Âthumb_insn_r->arm_mems[register_count].addr = start_address;
+ Â Â Â Â Âthumb_insn_r->arm_mems[register_count].len = 4;
+ Â Â Â Â Âstart_address = start_address + 4;
+ Â Â Â Â Âregister_count--;
+ Â Â Â Â}
+ Â Â Â Âthumb_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t) * 2);
+ Â Â Â Âthumb_insn_r->arm_regs[0] = 1;
+ Â Â Â Âthumb_insn_r->arm_regs[1] = ARM_SP_REGNUM;
+ Â Â}
+ Âelse if (0x1E == opcode1)
+ Â Â{
+ Â Â Â/* BKPT insn. Â*/
+ Â Â Â/* handle enhanced software breakpoint insn, BKPT. Â*/
+ Â Â Â/* CPSR is changed to be executed in ARM state, Âdisabling normal
+ Â Â Â Â Â Â Â interrupts, entering abort mode. Â*/
+ Â Â Â/* accorindly to high vector configuration PC is set accordingly. Â*/
+ Â Â Â/* Oza: FIX ME ? Âwhat if user hit breakpoint and type reverse, in
+ Â Â Â Â Â Â Â that case, we need to go back with previous CPSR and
+ Â Â Â Â Â Â Â Program Counter.. Â*/
+ Â Â Âthumb_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*3);
+ Â Â Âthumb_insn_r->arm_regs[0] = 2;
+ Â Â Âthumb_insn_r->arm_regs[1] = ARM_PS_REGNUM;
+ Â Â Âthumb_insn_r->arm_regs[2] = ARM_LR_REGNUM;
+ Â Â Â/* save SPSR also; how?. Â*/
+ Â Â}
+ Âelse if ((0 == opcode) || (1 == opcode))
+ Â Â{
+ Â Â Â /* ADD(5), ADD(6). Â*/
+ Â Â Âreg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
+ Â Â Âthumb_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*2);
+ Â Â Âthumb_insn_r->arm_regs[0] = 1;
+ Â Â Âthumb_insn_r->arm_regs[1] = reg_src1;
+ Â Â}
+ Âelse if (2 == opcode)
+ Â Â{
+ Â Â Â/* ADD(7), SUB(4). Â*/
+ Â Â Âreg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
+ Â Â Âthumb_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*2);
+ Â Â Âthumb_insn_r->arm_regs[0] = 1;
+ Â Â Âthumb_insn_r->arm_regs[1] = ARM_SP_REGNUM;
+ Â Â}
+
+
+ Âreturn 0;
+}
+
+static int
+thumb_handle_swi_insn (void *data)
+{
+
+ Âinsn_decode_record *thumb_insn_r = (insn_decode_record*) data;
+ Âstruct gdbarch_tdep *tdep = gdbarch_tdep (thumb_insn_r->gdbarch);
+ Âstruct regcache *reg_cache = (struct regcache*) thumb_insn_r->regcache;
+
+ Âuint32_t reg_val1 = 0;
+ Âuint32_t reg_src1 = 0;
+ Âuint32_t opcode1 = 0, opcode2 = 0, register_bits = 0, register_count = 0;
+ Âuint32_t register_list[8] = {0}, index = 0, start_address = 0;
+
+ Âunion
+ Â Â{
+ Â Â Âuint32_t s_word;
+ Â Â Âgdb_byte buf[4];
+ Â Â} u_buf;
+
+ Âopcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
+ Âopcode2 = bits (thumb_insn_r->arm_insn, 11, 12);
+
+ Âif (1 == opcode2)
+ Â Â{
+
+ Â Â Â/* LDMIA. Â*/
+ Â Â Âregister_bits = bits (thumb_insn_r->arm_insn, 0, 7);
+ Â Â Â/* get Rn. Â*/
+ Â Â Âreg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
+ Â Â Âwhile (register_bits)
+ Â Â Â Â{
+ Â Â Â Â Âif (register_bits & 0x00000001)
+ Â Â Â Â Â Âregister_list[register_count++] = 1;
+ Â Â Â Â Âregister_bits = register_bits >> 1;
+ Â Â Â Â}
+ Â Â Â Âthumb_insn_r->arm_regs = (uint32_t*)xmalloc \
+ Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â(sizeof(uint32_t) * (register_count +
2));
+ Â Â Â Âthumb_insn_r->arm_regs[0] = register_count + 1;
+ Â Â Â Âthumb_insn_r->arm_regs[register_count + 1] = reg_src1;
+ Â Â Âfor (register_count = 0; register_count < 8; register_count++)
+ Â Â Â Â{
+ Â Â Â Â Âif Â(register_list[register_count])
+ Â Â Â Â Â Â{
+ Â Â Â Â Â Â Âthumb_insn_r->arm_regs[index] = register_count;
+ Â Â Â Â Â Â Âindex++;
+ Â Â Â Â Â Â}
+ Â Â Â Â}
+ Â Â}
+ Âelse if (0 == opcode2)
+ Â Â{
+ Â Â Â/* it handles both STMIA. Â*/
+ Â Â Âregister_bits = bits (thumb_insn_r->arm_insn, 0, 7);
+ Â Â Â/* get Rn. Â*/
+ Â Â Âreg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
+ Â Â ÂGET_REG_VAL (reg_cache, reg_src1, &u_buf.buf[0]);
+ Â Â Âwhile (register_bits)
+ Â Â Â Â{
+ Â Â Â Â Âif (register_bits & 0x00000001)
+ Â Â Â Â Â Â register_count++;
+ Â Â Â Â Âregister_bits = register_bits >> 1;
+ Â Â Â Â}
+ Â Â Âstart_address = u_buf.s_word;
+ Â Â Âthumb_insn_r->arm_mems = (struct arm_mem_r *)xmalloc (sizeof(struct
+ Â Â Âarm_mem_r)*(register_count+1));
+ Â Â Âthumb_insn_r->arm_mems[0].len = register_count;
+ Â Â Âwhile (register_count)
+ Â Â Â Â{
+ Â Â Â Â Âthumb_insn_r->arm_mems[register_count].addr = start_address;
+ Â Â Â Â Âthumb_insn_r->arm_mems[register_count].len = 4;
+ Â Â Â Â Âstart_address = start_address + 4;
+ Â Â Â Â Âregister_count--;
+ Â Â Â Â}
+ Â Â}
+ Âelse if (0x1F == opcode1)
+ Â Â {
+ Â Â Â Â/* handle arm syscall insn. Â*/
+ Â Â Â Âif (tdep->arm_swi_record != NULL)
+ Â Â Â Â Â{
+ Â Â Â Â Â Âprintf("handling syscall swi insn\n");
+ Â Â Â Â Â Âtdep->arm_swi_record(reg_cache);
+ Â Â Â Â Â}
+ Â Â Â Âelse
+ Â Â Â Â Â{
+ Â Â Â Â Â Âreturn -1;
+ Â Â Â Â Â}
+ Â Â }
+
+ Â/* B(1), conditional branch is automatically taken care in process_record,
+ Â Â Â Âas PC is saved there. Â*/
+
+ Âreturn 0;
+}
+
+static int
+thumb_handle_branch_insn (void *data)
+{
+ Âinsn_decode_record *thumb_insn_r = (insn_decode_record*) data;
+ Âstruct gdbarch_tdep *tdep = gdbarch_tdep (thumb_insn_r->gdbarch);
+ Âstruct regcache *reg_cache = (struct regcache*) thumb_insn_r->regcache;
+
+ Âuint32_t reg_val1=0;
+ Âuint32_t reg_src1=0;
+ Âuint32_t opcode = 0, immed_5 = 0;
+
+ Âunion
+ Â Â{
+ Â Â Âuint32_t s_word;
+ Â Â Âgdb_byte buf[4];
+ Â Â} u_buf;
+
+
+ Â/* BL , BLX(1). Â*/
+ Âthumb_insn_r->arm_regs = (uint32_t*)xmalloc (sizeof(uint32_t)*3);
+ Âthumb_insn_r->arm_regs[0] = 2;
+ Âthumb_insn_r->arm_regs[1] = ARM_PS_REGNUM;
+ Âthumb_insn_r->arm_regs[2] = ARM_LR_REGNUM;
+
+ Â/* B(2) is automatically taken care in process_record, as PC is saved
+ Â Â Â Âthere. Â*/
+ Âreturn 0;
+}
+
+
+
+static int
+decode_insn (insn_decode_record *arm_record, uint32_t insn_size)
+{
+
+ Â/* (starting from numerical 0); bits 25, 26, 27 decodes type of arm
instruction. Â*/
+ Âint (*const arm_handle_insn[NO_OF_TYPE_OF_ARM_INSNS]) (void*) =
+ Â{
+ Â Â Âarm_handle_data_proc_misc_load_str_insn, Â/* 000. Â*/
+ Â Â Âarm_handle_data_proc_imm_insn, Â Â Â Â Â Â/* 001. Â*/
+ Â Â Âarm_handle_ld_st_imm_offset_insn, Â Â Â Â /* 010. Â*/
+ Â Â Âarm_handle_ld_st_reg_offset_insn, Â Â Â Â /* 011. Â*/
+ Â Â Âarm_hamdle_ld_st_multiple_insn, Â Â Â Â Â /* 100. Â*/
+ Â Â Âarm_handle_brn_insn, Â Â Â Â Â Â Â Â Â Â Â/* 101. Â*/
+ Â Â Âarm_handle_coproc_insn, Â Â Â Â Â Â Â Â Â /* 110. Â*/
+   Âarm_handle_coproc_data_proc_insn     Â/* 111. Â*/
+ Â};
+
+ Â/* (starting from numerical 0); bits 13,14,15 decodes type of thumb
instruction. Â*/
+ Âint (*const thumb_handle_insn[NO_OF_TYPE_OF_THUMB_INSNS]) (void*) =
+ Â{
+ Â Â Âthumb_handle_shift_add_sub_insn, Â Â Â Â /* 000. Â*/
+ Â Â Âthumb_handle_add_sub_cmp_mov_insn, Â Â Â /* 001. Â*/
+ Â Â Âthumb_handle_ld_st_reg_offset_insn, Â Â Â/* 010. Â*/
+ Â Â Âthumb_handle_ld_st_imm_offset_insn, Â Â Â/* 011. Â*/
+ Â Â Âthumb_hamdle_ld_st_stack_insn, Â Â Â Â Â /* 100. Â*/
+ Â Â Âthumb_handle_misc_insn, Â Â Â Â Â Â Â Â Â/* 101. Â*/
+ Â Â Âthumb_handle_swi_insn, Â Â Â Â Â Â Â Â Â /* 110. Â*/
+   Âthumb_handle_branch_insn         /* 111. Â*/
+ Â};
+
+ Âunion
+ Â Â{
+ Â Â Âuint32_t s_word;
+ Â Â Âgdb_byte buf[insn_size];
+ Â Â} u_buf;
+
+ Âuint32_t ret=0;
+
+ Âmemset (&u_buf, 0, sizeof(u_buf));
+ Âif (target_read_memory (arm_record->this_addr, &u_buf.buf[0], insn_size))
+ Â Â{
+ Â Â Âif (record_debug)
+ Â Â Â Â{
+ Â Â Â Â Âprintf_unfiltered (_("Process record: error reading memory at "
+ Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "addr %s len = %d.\n"),
+ Â Â Â Â Âpaddress (arm_record->gdbarch, arm_record->this_addr), insn_size);
+ Â Â Â Â Âreturn -1;
+ Â Â Â Â}
+ Â Â}
+ Âelse if (ARM_INSN_SIZE_BYTES == insn_size)
+ Â Â{
+ Â Â Âarm_record->arm_insn = u_buf.s_word;
+ Â Â Âarm_record->cond = bits (arm_record->arm_insn, 28, 31);
+ Â Â Âarm_record->id = bits (arm_record->arm_insn, 25, 27);
+ Â Â Âret = (0x0F != arm_record->cond)? \
+ Â Â Â Â Â Âarm_handle_insn[arm_record->id] ((void*)arm_record) : \
+ Â Â Â Â Â Âhandle_extension_space(arm_record);
+ Â Â}
+ Âelse if (THUMB_INSN_SIZE_BYTES == insn_size)
+ Â Â{
+ Â Â Âarm_record->arm_insn = u_buf.s_word;
+ Â Â Âarm_record->id = bits (arm_record->arm_insn, 13, 15);
+ Â Â Âret = thumb_handle_insn[arm_record->id] ((void*)arm_record);
+ Â Â}
+ Âreturn ret;
+}
+
+/* Parse the current instruction and record the values of the registers and
+ Â memory that will be changed in current instruction to "record_arch_list".
+ Â Return -1 if something is wrong.. Â*/
+
+int
+arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
+ Â Â Â Â Â Â Â Â Â Â Â Â Â Â CORE_ADDR insn_addr)
+{
+
+ Âenum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+ Âstruct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ Âuint32_t no_of_rec=0;
+ Âuint32_t ret=0;
+ ÂULONGEST t_bit = 0;
+
+ Âunion
+ Â Â{
+ Â Â Âuint32_t s_word;
+ Â Â Âgdb_byte buf[4];
+ Â Â} u_buf;
+
+ Âinsn_decode_record arm_record;
+ Âmemset (&u_buf, 0, sizeof(u_buf));
+
+ Âmemset (&arm_record, 0, sizeof (insn_decode_record));
+ Âarm_record.regcache = regcache;
+ Âarm_record.this_addr = insn_addr;
+ Âarm_record.gdbarch = gdbarch;
+
+
+ Âif (record_debug > 1)
+ Â Â{
+ Â Â Âfprintf_unfiltered (gdb_stdlog, "Process record: arm_process_record "
+ Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â"addr = %s\n",
+ Â Â Âpaddress (gdbarch, arm_record.this_addr));
+ Â Â}
+
+ Â/* check the insn, whether it is thumb or arm one. Â*/
+
+ Ât_bit = arm_psr_thumb_bit (arm_record.gdbarch);
+ ÂGET_REG_VAL (arm_record.regcache, ARM_PS_REGNUM, &u_buf.buf[0]);
+
+ Âif (!(u_buf.s_word & t_bit))
+ Â Â{
+ Â Â Â/* we are decoding arm insn. Â*/
+ Â Â Âret = decode_insn (&arm_record, ARM_INSN_SIZE_BYTES);
+ Â Â}
+ Âelse
+ Â Â{
+ Â Â Â/* we are decoding thumb insn. Â*/
+ Â Â Âret = decode_insn (&arm_record, THUMB_INSN_SIZE_BYTES);
+ Â Â}
+
+ Â/* record registers. Â*/
+ ÂARM_RECORD_ARCH_LIST_ADD_REG(ARM_PC_REGNUM);
+ Âif (arm_record.arm_regs)
+ Â Â{
+ Â Â Âfor (no_of_rec=1;no_of_rec<=arm_record.arm_regs[0];no_of_rec++)
+ Â Â Â Â{
+ Â Â Â Â Âif (ARM_RECORD_ARCH_LIST_ADD_REG (arm_record.arm_regs[no_of_rec]))
+ Â Â Â Â Âret = -1;
+ Â Â Â Â}
+ Â Â}
+ Â/* record memories. Â*/
+ Âif (arm_record.arm_mems)
+ Â Â{
+ Â Â Âfor (no_of_rec=1;no_of_rec<=arm_record.arm_mems[0].len;no_of_rec++)
+ Â Â Â {
+ Â Â Â Â Âif (record_arch_list_add_mem \
+ Â Â Â Â Â Â((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr,
+ Â Â Â Â Â Âarm_record.arm_mems[no_of_rec].len))
+ Â Â Â Â Â Âret = -1;
+ Â Â Â }
+ Â Â}
+
+ Âif (record_arch_list_add_end ())
+ Â Âret = -1;
+
+ Âif (arm_record.arm_regs)
+ Â Âxfree (arm_record.arm_regs);
+ Âif (arm_record.arm_mems)
+ Â Âxfree (arm_record.arm_mems);
+
+ Âreturn ret;
+}
diff -urN arm_orig/arm-tdep.h arm_new/arm-tdep.h
--- arm_orig/arm-tdep.h  Â2011-03-03 09:21:13.000000000 +0530
+++ arm_new/arm-tdep.h  Â2011-04-15 13:11:15.000000000 +0530
@@ -200,6 +200,9 @@
 /* Return the expected next PC if FRAME is stopped at a syscall
  Âinstruction. Â*/
 CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
+
+ Â /* Parse swi args. Â*/
+ Âint (*arm_swi_record) (struct regcache *regcache);
Â};

Â/* Structures used for displaced stepping. Â*/
@@ -310,6 +313,10 @@
           struct displaced_step_closure *,
           CORE_ADDR, CORE_ADDR, struct regcache *);

+extern int arm_process_record (struct gdbarch *gdbarch,
+ Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Âstruct regcache *regcache, CORE_ADDR addr);
+
+
Â/* Functions exported from armbsd-tdep.h. Â*/

Â/* Return the appropriate register set for the core section identified


----- Original Message ----
From: Yao Qi <yao@codesourcery.com>
To: gdb@sourceware.org
Sent: Mon, April 11, 2011 8:35:42 AM
Subject: Re: [PATCH] arm reversible : progress <phase_2_complete>

On 04/10/2011 05:41 PM, paawan oza wrote:
> Hi,
>
> phase2 (both arm and thumb insn implemenation is complete)
>
> Hi Tom:
> I have taken care of most of your comments: but could nit incorporate numercial
>
> to be replaced by some meaningful symbolic names.
> as I dont know what sort of symbolic names are approproate.
>
>

This one looks much better than previous ones. ÂThanks for working on
this. ÂI am not the people to approve this patch. ÂSome of my cents below.

> +
> +#define ARM_INSN_SIZE_BYTES 4
> +#define THUMB_INSN_SIZE_BYTES 2
> +#define NO_OF_TYPE_OF_ARM_INSNS 8
> +#define NO_OF_TYPE_OF_THUMB_INSNS 8
> +
> +#define ARM_RECORD_ARCH_LIST_ADD_REG(regnum) \
> + Â Ârecord_arch_list_add_reg (arm_record.regcache, regnum)
> +
> +#define GET_REG_VAL(REGCACHE,NO,BUF) Âregcache_raw_read (REGCACHE, NO, BUF);
> +
> +#define IS_IT_ARM_INSN(X) ((X & 0x00000020) >> 5)
> +#define ARM_PARSE_INSN(X,BIT_POS,NO_OF_BITS) \
> + Â Â Â Â Â Â Â Â((X >> (BIT_POS-1)) & (0xFFFFFFFF >> ((sizeof(uint32_t)*8) -
\
> + Â Â Â Â Â Â Â Â ÂNO_OF_BITS)))


There are some existing macros you can use for parsing instructions.

/* Support routines for instruction parsing. Â*/
#define submask(x) ((1L << ((x) + 1)) - 1)
#define bit(obj,st) (((obj) >> (st)) & 1)
#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
#define sbits(obj,st,fn) \
Â((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))

> +
> +#define INSN_S_L_BIT_NUM 21
> +#define ARM_BIT_SET(X, NUM) (((X >> (NUM-1)) & 0x00000001) == 1)
> +#define GET_BIT(X, NUM) (((X >> (NUM-1)) & 0x00000001))
> +

GET_BIT can be replaced by `bit' I posted above.

> +
> +static int
> +handle_extension_space (insn_decode_record *arm_record)
> +{
> + Âinsn_decode_record *arm_insn_r = arm_record;
> + Âstruct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch);
> + Âstruct regcache *reg_cache = arm_insn_r->regcache;
> +
> + Âuint32_t reg_src1 = 0, reg_src2 = 0;
> + Âuint32_t opcode1 = 0, opcode2 = 0;
> +
> + Âopcode1 = ARM_PARSE_INSN (arm_insn_r->arm_insn,26,3);
> + Âif ((3 == opcode1) && ARM_BIT_SET(arm_insn_r->arm_insn,5))
> + Â Â{
> + Â Â Â/* undefined instruction on ARM V5; need to handle if later versions
> + Â Â Â Â Âdefine it. Â*/
> + Â Â}
> +
> + Âopcode2 = ARM_PARSE_INSN (arm_insn_r->arm_insn,5,4);
> +
> + Âif ((!opcode1) && (9 == opcode2))
> + Â Â{
> + Â Â Â/* handle arithmetic insn extension space. Â*/
> + Â Â}
> +
> + Âopcode1 = ARM_PARSE_INSN (arm_insn_r->arm_insn,27,2);
                         ^ Â^
You need an extra space after each comma.

> + Âopcode2 = ARM_PARSE_INSN (arm_insn_r->arm_insn,24,2);
> +
> + Âif ((!opcode1) && (2 == opcode2) && !ARM_BIT_SET(arm_insn_r->arm_insn,21))
> + Â Â{
> + Â Â Â/* handle control insn extension space. Â*/
> + Â Â}
> +
> + Âopcode1 = ARM_PARSE_INSN (arm_insn_r->arm_insn,26,3);
> + Âif ((!opcode1) && (ARM_BIT_SET(arm_insn_r->arm_insn,8)) \
> + Â Â Â Â Â Â Â Â && (ARM_BIT_SET(arm_insn_r->arm_insn,5)))
> + Â Â{
> + Â Â Â/* handle load/store insn extension space. Â*/
> + Â Â}
> +
> + Âopcode1 = ARM_PARSE_INSN (arm_insn_r->arm_insn,24,5);
> + Âif ((24 == opcode1) && ARM_BIT_SET(arm_insn_r->arm_insn,22))
> + Â Â{
> + Â Â Â/* handle coprocessor insn extension space. Â*/
> + Â Â}
> +
> + Â/* to be done for ARMv5 and later; as of now we return -1. Â*/
> + Âreturn -1;
> +}
> +

> +
> +/* Parse the current instruction and record the values of the registers and
> + Â memory that will be changed in current instruction to "record_arch_list".
> + Â Return -1 if something is wrong.. Â*/
> +
> +int
> +arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â CORE_ADDR insn_addr)
> +{
> +
> + Âenum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
> + Âstruct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
> + Âuint32_t no_of_rec=0;
> + Âuint32_t ret=0;
> +
> + Âunion
> + Â Â{
> + Â Â Âuint32_t s_word;
> + Â Â Âgdb_byte buf[4];
> + Â Â} u_buf;
> +
> + Âinsn_decode_record arm_record;
> + Âmemset (&u_buf, 0, sizeof(u_buf));
> +
> + Âmemset (&arm_record, 0, sizeof (insn_decode_record));
> + Âarm_record.regcache = regcache;
> + Âarm_record.this_addr = insn_addr;
> + Âarm_record.gdbarch = gdbarch;
> +
> +
> + Âif (record_debug > 1)
> + Â Â{
> + Â Â Âfprintf_unfiltered (gdb_stdlog, "Process record: arm_process_record "
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â"addr = %s\n",
> + Â Â Âpaddress (gdbarch, arm_record.this_addr));
> + Â Â}
> +
> + Â/* check the insn, whether it is thumb or arm one. Â*/
> + ÂGET_REG_VAL (arm_record.regcache, ARM_PS_REGNUM, &u_buf.buf[0]);
> + Âarm_record.cond = ARM_PARSE_INSN (arm_record.arm_insn,29,4);
> +
> + Âif (!IS_IT_ARM_INSN (u_buf.s_word))

Please reference to `arm_frame_is_thumb' or `displaced_in_arm_mode' to
see how to check ARM mode or Thumb mode.

> + Â Â{
> + Â Â Â/* we are decoding arm insn. Â*/
> + Â Â Âret = decode_insn (&arm_record, ARM_INSN_SIZE_BYTES);
> + Â Â}
> + Âelse
> + Â Â{
> + Â Â Â/* we are decoding thumb insn. Â*/
> + Â Â Âret = decode_insn (&arm_record, THUMB_INSN_SIZE_BYTES);

On some ARM arch, there are 32-bit Thumb instructions, called Thumb-2.
Do you plan to support Thumb-2 insn?

> + Â Â}
> +
> + Â/* record registers. Â*/
> + ÂARM_RECORD_ARCH_LIST_ADD_REG(ARM_PC_REGNUM);
> + Âif (arm_record.arm_regs)
> + Â Â{
> + Â Â Âfor (no_of_rec=1;no_of_rec<=arm_record.arm_regs[0];no_of_rec++)
> + Â Â Â Â{
> + Â Â Â Â Âif (ARM_RECORD_ARCH_LIST_ADD_REG (arm_record.arm_regs[no_of_rec]))
> + Â Â Â Â Âret = -1;
> + Â Â Â Â}
> + Â Â}
> + Â/* record memories. Â*/
> + Âif (arm_record.arm_mems)
> + Â Â{
> + Â Â Âfor (no_of_rec=1;no_of_rec<=arm_record.arm_mems[0].len;no_of_rec++)
> + Â Â Â {
> + Â Â Â Â Âif (record_arch_list_add_mem \
> + Â Â Â Â Â Â((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr,
> + Â Â Â Â Â Âarm_record.arm_mems[no_of_rec].len))
> + Â Â Â Â Â Âret = -1;
> + Â Â Â }
> + Â Â}
> +
> + Âif (record_arch_list_add_end ())
> + Â Âret = -1;
> +
> + Âif (arm_record.arm_regs)
> + Â Âxfree (arm_record.arm_regs);
> + Âif (arm_record.arm_mems)
> + Â Âxfree (arm_record.arm_mems);
> +
> + Âreturn ret;
> +}

--
Yao (éå)