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[PATCH] sim: bfin: add GPIO device simulation
- From: Mike Frysinger <vapier at gentoo dot org>
- To: gdb-patches at sourceware dot org
- Cc: toolchain-devel at blackfin dot uclinux dot org
- Date: Tue, 15 Mar 2011 04:26:16 -0400
- Subject: [PATCH] sim: bfin: add GPIO device simulation
This takes care of the MMR interface and pushing up interrupts.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15 Mike Frysinger <vapier@gentoo.org>
* Makefile.in (dv-bfin_gpio.o): New target.
* configure.ac (SIM_AC_OPTION_HARDWARE): Add bfin_gpio.
* configure: Regenerate.
* dv-bfin_gpio.c, dv-bfin_gpio.h: New files.
* machs.c: Include dv-bfin_gpio.h.
(bf50x_mem, bf51x_mem, bf52x_mem, bf531_mem, bf532_mem, bf533_mem,
bf534_mem, bf536_mem, bf537_mem, bf538_mem, bf561_mem, bf592_mem):
Delete GPIO memory stubs.
(bf50x_dev, bf512_dev, bf516_dev, bf522_dev, bf526_dev, bf533_dev,
bf534_dev, bf537_dev, bf538_dev, bf561_dev, bf592_dev): Add GPIO
peripheral devices.
(bfin_model_hw_tree_init): Hook up GPIO interrupts to SIC.
---
sim/bfin/Makefile.in | 1 +
sim/bfin/configure | 1 +
sim/bfin/configure.ac | 1 +
sim/bfin/dv-bfin_gpio.c | 284 +++++++++++++++++++++++++++++++++++++++++++++++
sim/bfin/dv-bfin_gpio.h | 27 +++++
sim/bfin/machs.c | 65 ++++++-----
6 files changed, 351 insertions(+), 28 deletions(-)
create mode 100644 sim/bfin/dv-bfin_gpio.c
create mode 100644 sim/bfin/dv-bfin_gpio.h
diff --git a/sim/bfin/Makefile.in b/sim/bfin/Makefile.in
index 64f26d3..a20ae57 100644
--- a/sim/bfin/Makefile.in
+++ b/sim/bfin/Makefile.in
@@ -78,6 +78,7 @@ dv-bfin_ebiu_sdc.o: dv-bfin_ebiu_sdc.c devices.h $(INCLUDE)
dv-bfin_emac.o: dv-bfin_emac.c devices.h $(INCLUDE)
dv-bfin_eppi.o: dv-bfin_eppi.c devices.h $(INCLUDE)
dv-bfin_evt.o: dv-bfin_evt.c devices.h $(INCLUDE)
+dv-bfin_gpio.o: dv-bfin_gpio.c devices.h $(INCLUDE)
dv-bfin_gptimer.o: dv-bfin_gptimer.c devices.h $(INCLUDE)
dv-bfin_jtag.o: dv-bfin_jtag.c devices.h $(INCLUDE)
dv-bfin_mmu.o: dv-bfin_mmu.c devices.h $(INCLUDE)
diff --git a/sim/bfin/configure b/sim/bfin/configure
index ff71b59..02bfebb 100755
--- a/sim/bfin/configure
+++ b/sim/bfin/configure
@@ -5087,6 +5087,7 @@ hardware="$hardware \
bfin_emac \
bfin_eppi \
bfin_evt \
+ bfin_gpio \
bfin_gptimer \
bfin_jtag \
bfin_mmu \
diff --git a/sim/bfin/configure.ac b/sim/bfin/configure.ac
index 736a212..fddebc9 100644
--- a/sim/bfin/configure.ac
+++ b/sim/bfin/configure.ac
@@ -27,6 +27,7 @@ SIM_AC_OPTION_HARDWARE(yes,,\
bfin_emac \
bfin_eppi \
bfin_evt \
+ bfin_gpio \
bfin_gptimer \
bfin_jtag \
bfin_mmu \
diff --git a/sim/bfin/dv-bfin_gpio.c b/sim/bfin/dv-bfin_gpio.c
new file mode 100644
index 0000000..930c84a
--- /dev/null
+++ b/sim/bfin/dv-bfin_gpio.c
@@ -0,0 +1,284 @@
+/* Blackfin General Purpose Ports (GPIO) model
+
+ Copyright (C) 2010-2011 Free Software Foundation, Inc.
+ Contributed by Analog Devices, Inc.
+
+ This file is part of simulators.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#include "config.h"
+
+#include "sim-main.h"
+#include "devices.h"
+#include "dv-bfin_gpio.h"
+
+struct bfin_gpio
+{
+ bu32 base;
+
+ /* Order after here is important -- matches hardware MMR layout. */
+ bu16 BFIN_MMR_16(data);
+ bu16 BFIN_MMR_16(clear);
+ bu16 BFIN_MMR_16(set);
+ bu16 BFIN_MMR_16(toggle);
+ bu16 BFIN_MMR_16(maska);
+ bu16 BFIN_MMR_16(maska_clear);
+ bu16 BFIN_MMR_16(maska_set);
+ bu16 BFIN_MMR_16(maska_toggle);
+ bu16 BFIN_MMR_16(maskb);
+ bu16 BFIN_MMR_16(maskb_clear);
+ bu16 BFIN_MMR_16(maskb_set);
+ bu16 BFIN_MMR_16(maskb_toggle);
+ bu16 BFIN_MMR_16(dir);
+ bu16 BFIN_MMR_16(polar);
+ bu16 BFIN_MMR_16(edge);
+ bu16 BFIN_MMR_16(both);
+ bu16 BFIN_MMR_16(inen);
+};
+#define mmr_base() offsetof(struct bfin_gpio, data)
+#define mmr_offset(mmr) (offsetof(struct bfin_gpio, mmr) - mmr_base())
+
+static const char * const mmr_names[] = {
+ "PORTIO", "PORTIO_CLEAR", "PORTIO_SET", "PORTIO_TOGGLE", "PORTIO_MASKA",
+ "PORTIO_MASKA_CLEAR", "PORTIO_MASKA_SET", "PORTIO_MASKA_TOGGLE",
+ "PORTIO_MASKB", "PORTIO_MASKB_CLEAR", "PORTIO_MASKB_SET",
+ "PORTIO_MASKB_TOGGLE", "PORTIO_DIR", "PORTIO_POLAR", "PORTIO_EDGE",
+ "PORTIO_BOTH", "PORTIO_INEN",
+};
+#define mmr_name(off) mmr_names[(off) / 4]
+
+static unsigned
+bfin_gpio_io_write_buffer (struct hw *me, const void *source, int space,
+ address_word addr, unsigned nr_bytes)
+{
+ struct bfin_gpio *port = hw_data (me);
+ bu32 mmr_off;
+ bu16 value;
+ bu16 *valuep;
+
+ value = dv_load_2 (source);
+ mmr_off = addr - port->base;
+ valuep = (void *)((unsigned long)port + mmr_base() + mmr_off);
+
+ HW_TRACE_WRITE ();
+
+ dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
+
+ switch (mmr_off)
+ {
+ case mmr_offset(data):
+ case mmr_offset(maska):
+ case mmr_offset(maskb):
+ case mmr_offset(dir):
+ case mmr_offset(polar):
+ case mmr_offset(edge):
+ case mmr_offset(both):
+ case mmr_offset(inen):
+ *valuep = value;
+ break;
+ case mmr_offset(clear):
+ case mmr_offset(maska_clear):
+ case mmr_offset(maskb_clear):
+ dv_w1c_2 (valuep, value, 0);
+ break;
+ case mmr_offset(set):
+ case mmr_offset(maska_set):
+ case mmr_offset(maskb_set):
+ *valuep |= value;
+ break;
+ case mmr_offset(toggle):
+ case mmr_offset(maska_toggle):
+ case mmr_offset(maskb_toggle):
+ *valuep ^= value;
+ break;
+ default:
+ dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
+ break;
+ }
+
+ return nr_bytes;
+}
+
+static unsigned
+bfin_gpio_io_read_buffer (struct hw *me, void *dest, int space,
+ address_word addr, unsigned nr_bytes)
+{
+ struct bfin_gpio *port = hw_data (me);
+ bu32 mmr_off;
+ bu16 *valuep;
+
+ mmr_off = addr - port->base;
+ valuep = (void *)((unsigned long)port + mmr_base() + mmr_off);
+
+ HW_TRACE_READ ();
+
+ dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
+
+ switch (mmr_off)
+ {
+ case mmr_offset(data):
+ case mmr_offset(clear):
+ case mmr_offset(set):
+ case mmr_offset(toggle):
+ dv_store_2 (dest, port->data);
+ break;
+ case mmr_offset(maska):
+ case mmr_offset(maska_clear):
+ case mmr_offset(maska_set):
+ case mmr_offset(maska_toggle):
+ dv_store_2 (dest, port->maska);
+ break;
+ case mmr_offset(maskb):
+ case mmr_offset(maskb_clear):
+ case mmr_offset(maskb_set):
+ case mmr_offset(maskb_toggle):
+ dv_store_2 (dest, port->maskb);
+ break;
+ case mmr_offset(dir):
+ case mmr_offset(polar):
+ case mmr_offset(edge):
+ case mmr_offset(both):
+ case mmr_offset(inen):
+ dv_store_2 (dest, *valuep);
+ break;
+ default:
+ dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
+ break;
+ }
+
+ return nr_bytes;
+}
+
+static const struct hw_port_descriptor bfin_gpio_ports[] = {
+ { "mask_a", 0, 0, output_port, },
+ { "mask_b", 1, 0, output_port, },
+ { "p0", 0, 0, input_port, },
+ { "p1", 1, 0, input_port, },
+ { "p2", 2, 0, input_port, },
+ { "p3", 3, 0, input_port, },
+ { "p4", 4, 0, input_port, },
+ { "p5", 5, 0, input_port, },
+ { "p6", 6, 0, input_port, },
+ { "p7", 7, 0, input_port, },
+ { "p8", 8, 0, input_port, },
+ { "p9", 9, 0, input_port, },
+ { "p10", 10, 0, input_port, },
+ { "p11", 11, 0, input_port, },
+ { "p12", 12, 0, input_port, },
+ { "p13", 13, 0, input_port, },
+ { "p14", 14, 0, input_port, },
+ { NULL, 0, 0, 0, },
+};
+
+static void
+bfin_gpio_port_event (struct hw *me, int my_port, struct hw *source,
+ int source_port, int level)
+{
+ struct bfin_gpio *port = hw_data (me);
+ bool olvl, nlvl;
+ bu32 bit = (1 << my_port);
+
+ /* Only screw with state if this pin is set as an input. */
+ if (!(port->dir & port->inen & bit))
+ return;
+
+ /* Get the old pin state for calculating an interrupt. */
+ olvl = !!(port->data & bit);
+
+ /* Update the new pin state. */
+ port->data = (port->data & ~bit) | (level << bit);
+
+ /* See if this state transition will generate an interrupt. */
+ nlvl = !!(port->data & bit);
+
+ if (port->edge & bit)
+ {
+ /* Pin is edge triggered. */
+ if (!(port->both & bit))
+ {
+ /* Both edges. */
+ if (olvl == nlvl)
+ return;
+ }
+ else
+ {
+ /* Just one edge. */
+ if (!(((port->polar & bit) && olvl > nlvl)
+ || (!(port->polar & bit) && olvl < nlvl)))
+ return;
+ }
+ }
+ else
+ {
+ /* Pin is level triggered. */
+ if (nlvl == !!(port->polar & bit))
+ return;
+ }
+
+ /* If the masks allow it, push the interrupt even higher. */
+ if (port->maska & bit)
+ hw_port_event (me, 0, 1);
+ if (port->maskb & bit)
+ hw_port_event (me, 1, 1);
+}
+
+static void
+attach_bfin_gpio_regs (struct hw *me, struct bfin_gpio *port)
+{
+ address_word attach_address;
+ int attach_space;
+ unsigned attach_size;
+ reg_property_spec reg;
+
+ if (hw_find_property (me, "reg") == NULL)
+ hw_abort (me, "Missing \"reg\" property");
+
+ if (!hw_find_reg_array_property (me, "reg", 0, ®))
+ hw_abort (me, "\"reg\" property must contain three addr/size entries");
+
+ hw_unit_address_to_attach_address (hw_parent (me),
+ ®.address,
+ &attach_space, &attach_address, me);
+ hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
+
+ if (attach_size != BFIN_MMR_GPIO_SIZE)
+ hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_GPIO_SIZE);
+
+ hw_attach_address (hw_parent (me),
+ 0, attach_space, attach_address, attach_size, me);
+
+ port->base = attach_address;
+}
+
+static void
+bfin_gpio_finish (struct hw *me)
+{
+ struct bfin_gpio *port;
+
+ port = HW_ZALLOC (me, struct bfin_gpio);
+
+ set_hw_data (me, port);
+ set_hw_io_read_buffer (me, bfin_gpio_io_read_buffer);
+ set_hw_io_write_buffer (me, bfin_gpio_io_write_buffer);
+ set_hw_ports (me, bfin_gpio_ports);
+ set_hw_port_event (me, bfin_gpio_port_event);
+
+ attach_bfin_gpio_regs (me, port);
+}
+
+const struct hw_descriptor dv_bfin_gpio_descriptor[] = {
+ {"bfin_gpio", bfin_gpio_finish,},
+ {NULL, NULL},
+};
diff --git a/sim/bfin/dv-bfin_gpio.h b/sim/bfin/dv-bfin_gpio.h
new file mode 100644
index 0000000..c73ca35
--- /dev/null
+++ b/sim/bfin/dv-bfin_gpio.h
@@ -0,0 +1,27 @@
+/* Blackfin General Purpose Ports (GPIO) model
+
+ Copyright (C) 2010-2011 Free Software Foundation, Inc.
+ Contributed by Analog Devices, Inc.
+
+ This file is part of simulators.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#ifndef DV_BFIN_GPIO_H
+#define DV_BFIN_GPIO_H
+
+/* XXX: This should be pushed into the model data. */
+#define BFIN_MMR_GPIO_SIZE (17 * 4)
+
+#endif
diff --git a/sim/bfin/machs.c b/sim/bfin/machs.c
index e60e8c9..6f33385 100644
--- a/sim/bfin/machs.c
+++ b/sim/bfin/machs.c
@@ -36,13 +36,14 @@
#include "dv-bfin_emac.h"
#include "dv-bfin_eppi.h"
#include "dv-bfin_evt.h"
+#include "dv-bfin_gpio.h"
#include "dv-bfin_gptimer.h"
#include "dv-bfin_jtag.h"
#include "dv-bfin_mmu.h"
#include "dv-bfin_nfc.h"
#include "dv-bfin_otp.h"
-#include "dv-bfin_ppi.h"
#include "dv-bfin_pll.h"
+#include "dv-bfin_ppi.h"
#include "dv-bfin_rtc.h"
#include "dv-bfin_sic.h"
#include "dv-bfin_spi.h"
@@ -95,11 +96,8 @@ static const struct bfin_dmac_layout bf000_dmac[] = {};
#define bf504_chipid bf50x_chipid
#define bf506_chipid bf50x_chipid
static const struct bfin_memory_layout bf50x_mem[] = {
- LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */
LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
- LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */
- LAYOUT (0xFFC01700, 0x50, read_write), /* PORTH stub */
LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
LAYOUT (0xFFC03800, 0x100, read_write), /* RSI stub */
LAYOUT (0xFFC0328C, 0xC, read_write), /* Flash stub */
@@ -122,9 +120,12 @@ static const struct bfin_dev_layout bf50x_dev[] = {
DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
+ DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
DEVICE (0xFFC00A00, BF50X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
+ DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
+ DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
};
@@ -143,11 +144,8 @@ static const struct bfin_dmac_layout bf50x_dmac[] = {
#define bf518_chipid bf51x_chipid
static const struct bfin_memory_layout bf51x_mem[] = {
LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
- LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */
LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
- LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */
- LAYOUT (0xFFC01700, 0x50, read_write), /* PORTH stub */
LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
LAYOUT (0xFFC03800, 0xD0, read_write), /* RSI stub */
LAYOUT (0xFFC03FE0, 0x20, read_write), /* RSI peripheral stub */
@@ -175,10 +173,13 @@ static const struct bfin_dev_layout bf512_dev[] = {
DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
+ DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
+ DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
+ DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
@@ -197,10 +198,13 @@ static const struct bfin_dev_layout bf516_dev[] = {
DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
+ DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
+ DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
+ DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
DEVICE (0, 0x20, "bfin_emac/eth_phy"),
@@ -221,11 +225,8 @@ static const struct bfin_dev_layout bf516_dev[] = {
#define bf527_chipid bf523_chipid
static const struct bfin_memory_layout bf52x_mem[] = {
LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
- LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */
LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
- LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */
- LAYOUT (0xFFC01700, 0x50, read_write), /* PORTH stub */
LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
LAYOUT (0xFFC03800, 0x500, read_write), /* MUSB stub */
LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
@@ -255,10 +256,13 @@ static const struct bfin_dev_layout bf522_dev[] = {
DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
+ DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
+ DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
+ DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
@@ -279,10 +283,13 @@ static const struct bfin_dev_layout bf526_dev[] = {
DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
+ DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
+ DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
+ DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
DEVICE (0, 0x20, "bfin_emac/eth_phy"),
@@ -302,7 +309,6 @@ static const struct bfin_dev_layout bf526_dev[] = {
#define bf533_chipid bf531_chipid
static const struct bfin_memory_layout bf531_mem[] = {
LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
- LAYOUT (0xFFC00700, 0x50, read_write), /* GPIO stub */
LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
@@ -311,7 +317,6 @@ static const struct bfin_memory_layout bf531_mem[] = {
};
static const struct bfin_memory_layout bf532_mem[] = {
LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
- LAYOUT (0xFFC00700, 0x50, read_write), /* GPIO stub */
LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
@@ -322,7 +327,6 @@ static const struct bfin_memory_layout bf532_mem[] = {
};
static const struct bfin_memory_layout bf533_mem[] = {
LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
- LAYOUT (0xFFC00700, 0x50, read_write), /* GPIO stub */
LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
@@ -342,6 +346,7 @@ static const struct bfin_dev_layout bf533_dev[] = {
DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
+ DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
@@ -359,11 +364,8 @@ static const struct bfin_dmac_layout bf533_dmac[] = {
#define bf537_chipid bf536_chipid
static const struct bfin_memory_layout bf534_mem[] = {
LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
- LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */
LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
- LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */
- LAYOUT (0xFFC01700, 0x50, read_write), /* PORTH stub */
LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
@@ -375,11 +377,8 @@ static const struct bfin_memory_layout bf534_mem[] = {
};
static const struct bfin_memory_layout bf536_mem[] = {
LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
- LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */
LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
- LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */
- LAYOUT (0xFFC01700, 0x50, read_write), /* PORTG stub */
LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
@@ -389,11 +388,8 @@ static const struct bfin_memory_layout bf536_mem[] = {
};
static const struct bfin_memory_layout bf537_mem[] = {
LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
- LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */
LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
- LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */
- LAYOUT (0xFFC01700, 0x50, read_write), /* PORTG stub */
LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
@@ -416,10 +412,13 @@ static const struct bfin_dev_layout bf534_dev[] = {
DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
+ DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
+ DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
+ DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
};
static const struct bfin_dev_layout bf537_dev[] = {
@@ -435,10 +434,13 @@ static const struct bfin_dev_layout bf537_dev[] = {
DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
+ DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
+ DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
+ DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
DEVICE (0, 0x20, "bfin_emac/eth_phy"),
@@ -451,7 +453,6 @@ static const struct bfin_dev_layout bf537_dev[] = {
#define bf538_chipid 0x27c4
#define bf539_chipid bf538_chipid
static const struct bfin_memory_layout bf538_mem[] = {
- LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */
LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
LAYOUT (0xFFC01500, 0x70, read_write), /* PORTC/D/E stub */
@@ -479,6 +480,7 @@ static const struct bfin_dev_layout bf538_dev[] = {
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
+ DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
_DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1", 1),
_DEVICE (0xFFC02100, BFIN_MMR_UART_SIZE, "bfin_uart@2", 1),
DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
@@ -621,11 +623,8 @@ static const struct bfin_dmac_layout bf54x_dmac[] = {
/* This is only Core A of course ... */
#define bf561_chipid 0x27bb
static const struct bfin_memory_layout bf561_mem[] = {
- LAYOUT (0xFFC00700, 0x50, read_write), /* GPIO0 stub */
LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
- LAYOUT (0xFFC01500, 0x50, read_write), /* GPIO1 stub */
- LAYOUT (0xFFC01700, 0x50, read_write), /* GPIO2 stub */
LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */
LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
@@ -646,15 +645,18 @@ static const struct bfin_dev_layout bf561_dev[] = {
DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
+ DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
_DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0", 1),
DEVICE (0xFFC01200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@1"),
_DEVICE (0xFFC01300, BFIN_MMR_PPI_SIZE, "bfin_ppi@1", 1),
+ DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@11"),
+ DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
};
static const struct bfin_dmac_layout bf561_dmac[] = {
{ BFIN_MMR_DMAC0_BASE, 12, },
@@ -664,10 +666,8 @@ static const struct bfin_dmac_layout bf561_dmac[] = {
#define bf592_chipid 0x20cb
static const struct bfin_memory_layout bf592_mem[] = {
- LAYOUT (0xFFC00700, 0x50, read_write), /* GPIO0 stub */
LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
- LAYOUT (0xFFC01500, 0x50, read_write), /* GPIO1 stub */
LAYOUT (0xFF800000, 0x8000, read_write), /* Data A */
LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst B [1] */
@@ -679,9 +679,11 @@ static const struct bfin_dev_layout bf592_dev[] = {
DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
+ DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
DEVICE (0xFFC01300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
+ DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
};
static const struct bfin_dmac_layout bf592_dmac[] = {
/* XXX: there are only 9 channels, but mdma code below assumes that they
@@ -820,6 +822,13 @@ bfin_model_hw_tree_init (SIM_DESC sd, SIM_CPU *cpu)
sim_hw_parse (sd, "/core/%s > nmi nmi /core/bfin_cec", dev->dev);
sim_hw_parse (sd, "/core/%s > gpi wdog /core/bfin_sic", dev->dev);
}
+ else if (!strncmp (dev->dev, "bfin_gpio", 9))
+ {
+ sim_hw_parse (sd, "/core/%s > mask_a port%c_irq_a /core/bfin_sic",
+ dev->dev, dev->dev[10]);
+ sim_hw_parse (sd, "/core/%s > mask_b port%c_irq_b /core/bfin_sic",
+ dev->dev, dev->dev[10]);
+ }
}
done:
--
1.7.4.1