This is the mail archive of the
gdb-patches@sourceware.org
mailing list for the GDB project.
Re: [PATCH-ppc 5/5] Add VSX doc bits
- From: Luis Machado <luisgpm at linux dot vnet dot ibm dot com>
- To: Eli Zaretskii <eliz at gnu dot org>
- Cc: gdb-patches at sourceware dot org
- Date: Fri, 15 Aug 2008 15:12:56 -0300
- Subject: Re: [PATCH-ppc 5/5] Add VSX doc bits
- References: <1217016956.29012.79.camel@gargoyle> <1218814096.8946.39.camel@gargoyle> <uzlnedx87.fsf@gnu.org>
- Reply-to: luisgpm at linux dot vnet dot ibm dot com
On Fri, 2008-08-15 at 20:06 +0300, Eli Zaretskii wrote:
> This needs to state the node name where the changes are made.
> This is OK, modulo Stan's comments on using "new".
Both should be addressed in the patch below.
Thanks,
Luis
---
2008-08-15 Luis Machado <luisgpm@br.ibm.com>
* doc/gdb.texinfo (PowerPC): Mention Extended FPR's for POWER7.
(PowerPC features): Mention feature set for VSX registers.
Index: gdb/doc/gdb.texinfo
===================================================================
--- gdb.orig/doc/gdb.texinfo 2008-08-15 07:02:10.000000000 -0700
+++ gdb/doc/gdb.texinfo 2008-08-15 08:50:00.000000000 -0700
@@ -16427,6 +16427,9 @@
by joining the even/odd register pairs @code{f0} and @code{f1} for @code{$dl0},
@code{f2} and @code{f3} for @code{$dl1} and so on.
+For POWER7 processors, GDB provides a set of pseudo-registers, the 64-bit
+wide Extended Floating Point Registers (@samp{f32} through @samp{f63}).
+
@node Controlling GDB
@chapter Controlling @value{GDBN}
@@ -27865,6 +27868,13 @@
contain registers @samp{vr0} through @samp{vr31}, @samp{vscr},
and @samp{vrsave}.
+The @samp{org.gnu.gdb.power.vsx} feature is optional. It should
+contain registers @samp{vs0h} through @samp{vs31h}. @value{GDBN}
+will combine these registers with the floating point registers
+(@samp{f0} through @samp{f31}) and the altivec registers (@samp{vr0}
+through @samp{vr31}} to present the 128-bit wide registers @samp{vs0}
+through @samp{vs63}, the set of vector registers for POWER7.
+
The @samp{org.gnu.gdb.power.spe} feature is optional. It should
contain registers @samp{ev0h} through @samp{ev31h}, @samp{acc}, and
@samp{spefscr}. SPE targets should provide 32-bit registers in