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Re: [patch] Fix ll, sc and swxc1 for the 32-bit MIPS simulator
- From: Daniel Jacobowitz <drow at false dot org>
- To: gdb-patches at sourceware dot org, rsandifo at nildram dot co dot uk
- Date: Sun, 7 Oct 2007 00:43:07 -0400
- Subject: Re: [patch] Fix ll, sc and swxc1 for the 32-bit MIPS simulator
- References: <87k5q5v5pg.fsf@firetop.home>
On Tue, Oct 02, 2007 at 05:31:23PM +0100, Richard Sandiford wrote:
> mips.igen's handling of ll, sc and swxc1 is currently hardwired
> for WITH_TARGET_WORD_BITSIZE == 64. The patch below fixes this
> by using the same constructs as other loads and stores. It cures
> gcc.target/mips/atomic-memory-1.c for mipsisa32-elf and introduces
> no regressions. OK to install?
>
> Richard
>
>
> sim/mips/
> * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
> (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
> shifts for that case.
OK, thanks.
--
Daniel Jacobowitz
CodeSourcery