This is the mail archive of the
gdb-patches@sourceware.org
mailing list for the GDB project.
[patch] arm-sim on 64-bit hosts.
- From: Paul Brook <paul at codesourcery dot com>
- To: gdb-patches at sources dot redhat dot com
- Date: Sun, 11 Sep 2005 22:56:16 +0100
- Subject: [patch] arm-sim on 64-bit hosts.
The attached patch fixes the gdb Arm simulator on 64-bit hosts. Two problems:
- "long" was assumed to be a 32-bit type.
- ARMul_MemoryInit used the wrong type calculating the size of the pagetables.
Ok?
Paul
2005-09-11 Paul Brook <paul@codesourcery.com>
* arm/armdefs.h: Define ARMsword and ARMsdword. Use stdint.h when available.
* arm/armemu.c: Use them.
* arm/armvirt.c (ARMul_MemoryInit): Use correct type for size.
* arm/configure.ac: Check for stdint.h.
* arm/config.in: Regenerate.
* arm/configure: Regenerate.
Index: sim/arm/armdefs.h
===================================================================
RCS file: /cvs/src/src/sim/arm/armdefs.h,v
retrieving revision 1.13
diff -u -p -r1.13 armdefs.h
--- sim/arm/armdefs.h 12 May 2005 07:36:58 -0000 1.13
+++ sim/arm/armdefs.h 11 Sep 2005 19:51:41 -0000
@@ -15,6 +15,7 @@
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+#include "config.h"
#include <stdio.h>
#include <stdlib.h>
@@ -29,8 +30,18 @@
typedef char *VoidStar;
#endif
-typedef unsigned long ARMword; /* must be 32 bits wide */
+#ifdef HAVE_STDINT_H
+#include <stdint.h>
+typedef uint32_t ARMword;
+typedef int32_t ARMsword;
+typedef uint64_t ARMdword;
+typedef int64_t ARMsdword;
+#else
+typedef unsigned int ARMword; /* must be 32 bits wide */
+typedef signed int ARMsword;
typedef unsigned long long ARMdword; /* Must be at least 64 bits wide. */
+typedef signed long long ARMsdword;
+#endif
typedef struct ARMul_State ARMul_State;
typedef unsigned ARMul_CPInits (ARMul_State * state);
Index: sim/arm/armemu.c
===================================================================
RCS file: /cvs/src/src/sim/arm/armemu.c,v
retrieving revision 1.33
diff -u -p -r1.33 armemu.c
--- sim/arm/armemu.c 12 May 2005 07:36:58 -0000 1.33
+++ sim/arm/armemu.c 11 Sep 2005 19:51:41 -0000
@@ -1584,9 +1584,9 @@ check_PMUintr:
&& (BIT (5) == 0 || BITS (12, 15) == 0))
{
/* ElSegundo SMLAWy/SMULWy insn. */
- unsigned long long op1 = state->Reg[BITS (0, 3)];
- unsigned long long op2 = state->Reg[BITS (8, 11)];
- unsigned long long result;
+ ARMdword op1 = state->Reg[BITS (0, 3)];
+ ARMdword op2 = state->Reg[BITS (8, 11)];
+ ARMdword result;
if (BIT (6))
op2 >>= 16;
@@ -1733,10 +1733,10 @@ check_PMUintr:
if (BIT (4) == 0 && BIT (7) == 1)
{
/* ElSegundo SMLALxy insn. */
- unsigned long long op1 = state->Reg[BITS (0, 3)];
- unsigned long long op2 = state->Reg[BITS (8, 11)];
- unsigned long long dest;
- unsigned long long result;
+ ARMdword op1 = state->Reg[BITS (0, 3)];
+ ARMdword op2 = state->Reg[BITS (8, 11)];
+ ARMdword dest;
+ ARMdword result;
if (BIT (5))
op1 >>= 16;
@@ -1749,7 +1749,7 @@ check_PMUintr:
if (op2 & 0x8000)
op2 -= 65536;
- dest = (unsigned long long) state->Reg[BITS (16, 19)] << 32;
+ dest = (ARMdword) state->Reg[BITS (16, 19)] << 32;
dest |= state->Reg[BITS (12, 15)];
dest += op1 * op2;
state->Reg[BITS (12, 15)] = dest;
@@ -3684,8 +3684,8 @@ check_PMUintr:
{
/* XScale MIA instruction. Signed multiplication of
two 32 bit values and addition to 40 bit accumulator. */
- long long Rm = state->Reg[MULLHSReg];
- long long Rs = state->Reg[MULACCReg];
+ ARMsdword Rm = state->Reg[MULLHSReg];
+ ARMsdword Rs = state->Reg[MULACCReg];
if (Rm & (1 << 31))
Rm -= 1ULL << 32;
@@ -3704,7 +3704,7 @@ check_PMUintr:
ARMword t2 = state->Reg[MULACCReg] >> 16;
ARMword t3 = state->Reg[MULLHSReg] & 0xffff;
ARMword t4 = state->Reg[MULACCReg] & 0xffff;
- long long t5;
+ ARMsdword t5;
if (t1 & (1 << 15))
t1 -= 1 << 16;
@@ -3734,7 +3734,7 @@ check_PMUintr:
/* XScale MIAxy instruction. */
ARMword t1;
ARMword t2;
- long long t5;
+ ARMsdword t5;
if (BIT (17))
t1 = state->Reg[MULLHSReg] >> 16;
@@ -3926,9 +3926,9 @@ GetDPRegRHS (ARMul_State * state, ARMwor
if (shamt == 0)
return (base);
else if (shamt >= 32)
- return ((ARMword) ((long int) base >> 31L));
+ return ((ARMword) ((ARMsword) base >> 31L));
else
- return ((ARMword) ((long int) base >> (int) shamt));
+ return ((ARMword) ((ARMsword) base >> (int) shamt));
case ROR:
shamt &= 0x1f;
if (shamt == 0)
@@ -3958,9 +3958,9 @@ GetDPRegRHS (ARMul_State * state, ARMwor
return (base >> shamt);
case ASR:
if (shamt == 0)
- return ((ARMword) ((long int) base >> 31L));
+ return ((ARMword) ((ARMsword) base >> 31L));
else
- return ((ARMword) ((long int) base >> (int) shamt));
+ return ((ARMword) ((ARMsword) base >> (int) shamt));
case ROR:
if (shamt == 0)
/* It's an RRX. */
@@ -4041,12 +4041,12 @@ GetDPSRegRHS (ARMul_State * state, ARMwo
else if (shamt >= 32)
{
ASSIGNC (base >> 31L);
- return ((ARMword) ((long int) base >> 31L));
+ return ((ARMword) ((ARMsword) base >> 31L));
}
else
{
- ASSIGNC ((ARMword) ((long int) base >> (int) (shamt - 1)) & 1);
- return ((ARMword) ((long int) base >> (int) shamt));
+ ASSIGNC ((ARMword) ((ARMsword) base >> (int) (shamt - 1)) & 1);
+ return ((ARMword) ((ARMsword) base >> (int) shamt));
}
case ROR:
if (shamt == 0)
@@ -4095,12 +4095,12 @@ GetDPSRegRHS (ARMul_State * state, ARMwo
if (shamt == 0)
{
ASSIGNC (base >> 31L);
- return ((ARMword) ((long int) base >> 31L));
+ return ((ARMword) ((ARMsword) base >> 31L));
}
else
{
- ASSIGNC ((ARMword) ((long int) base >> (int) (shamt - 1)) & 1);
- return ((ARMword) ((long int) base >> (int) shamt));
+ ASSIGNC ((ARMword) ((ARMsword) base >> (int) (shamt - 1)) & 1);
+ return ((ARMword) ((ARMsword) base >> (int) shamt));
}
case ROR:
if (shamt == 0)
@@ -4239,9 +4239,9 @@ GetLSRegRHS (ARMul_State * state, ARMwor
return (base >> shamt);
case ASR:
if (shamt == 0)
- return ((ARMword) ((long int) base >> 31L));
+ return ((ARMword) ((ARMsword) base >> 31L));
else
- return ((ARMword) ((long int) base >> (int) shamt));
+ return ((ARMword) ((ARMsword) base >> (int) shamt));
case ROR:
if (shamt == 0)
/* It's an RRX. */
@@ -5086,10 +5086,10 @@ Multiply64 (ARMul_State * state, ARMword
/* Compute sign of result and adjust operands if necessary. */
sign = (Rm ^ Rs) & 0x80000000;
- if (((signed long) Rm) < 0)
+ if (((ARMsword) Rm) < 0)
Rm = -Rm;
- if (((signed long) Rs) < 0)
+ if (((ARMsword) Rs) < 0)
Rs = -Rs;
}
Index: sim/arm/armvirt.c
===================================================================
RCS file: /cvs/src/src/sim/arm/armvirt.c,v
retrieving revision 1.10
diff -u -p -r1.10 armvirt.c
--- sim/arm/armvirt.c 12 May 2005 07:36:59 -0000 1.10
+++ sim/arm/armvirt.c 11 Sep 2005 19:51:41 -0000
@@ -139,7 +139,7 @@ ARMul_MemoryInit (ARMul_State * state, u
if (initmemsize)
state->MemSize = initmemsize;
- pagetable = (ARMword **) malloc (sizeof (ARMword) * NUMPAGES);
+ pagetable = (ARMword **) malloc (sizeof (ARMword *) * NUMPAGES);
if (pagetable == NULL)
return FALSE;
Index: sim/arm/configure.ac
===================================================================
RCS file: /cvs/src/src/sim/arm/configure.ac,v
retrieving revision 1.3
diff -u -p -r1.3 configure.ac
--- sim/arm/configure.ac 14 Jan 2005 20:05:38 -0000 1.3
+++ sim/arm/configure.ac 11 Sep 2005 19:51:41 -0000
@@ -9,7 +9,7 @@ sinclude(../common/aclocal.m4)
# it by inlining the macro's contents.
sinclude(../common/common.m4)
-AC_CHECK_HEADERS(unistd.h)
+AC_CHECK_HEADERS(unistd.h stdint.h)
COPRO="armcopro.o maverick.o iwmmxt.o"