Update ARM simulator to handle ARMv6 zero/sign extendinginstructions

[Nick Clifton <nickc at redhat dot com>]

Hi Guys,

  I am applying the patch below to upgrade the ARM simulator so that
  it can handle some of the zero- and sign- extending instructions
  introduced into the ARMv6 instruction set.  Specifically the
  simulator can now handle:

     UXB, UXTAB, UXH, UXAH, SXB, SXAB, SXH, SXAH

  Coincidentally these are the instructions that GCC will now generate
  automatically when compiling for a v6 target, so this patch means
  that it is now possible to use the simulator to run the GCC
  testsuite for am ARMv6 target.

Cheers
  Nick

sim/arm/ChangeLog
2005-04-20  Nick Clifton  <nickc@redhat.com>

	* armemu.c (handle_v6_insn): New function - emulate a few of the
	v6 instructions - the ones now generated by GCC.
	(ARMulEmulate32): Call handle_v6_insn when a possible v6 insn is
	found.
	* armdefs.h (struct ARMul_State): Add new field: is_v6.
	(ARM_v6_Prop): Define.
	* arminit.c (ARMul_NewState): Initialise the v6 flag.
	(ARMul_SelectProcessor): Determine if the v6 flag should be
	set.
	* wrapper.c (sim_create_inferior): For unknown architectures,
	default to allowing the v6 instructions.

Attachment: arm.sim.patch.bz2
Description: BZip2 compressed data