Hmmm? I thought 'L' was for registers, and 'MA' was for memory access.
This is the only instruction that modifies a gpr but doesn't call 'L'.
Figured it was an oversight.
No, MA is for the memory *access conflict* between data access and
instruction fetch for the non/unified cache SH[123], while L is for
the memory access *latency* on SH[123].
And, of course, there is also no L for "mov <REG_M>,<REG_N>".
Actually I was just going for consistancy (everywhere else that
modifies nip uses SET_NIP). I'll gladly drop this part of the
patch if you don't like it.
Well, I don't like it because it adds more code unnecessarily, thus
increasing the working set.
And it isn't really inconsistent; SET_NIP is used when nip is changed
for something other than linear instruction fetch, so that we know
if we'll sooner hit a loop boundary or the end of memory.
ppi_insn and the profile trap just do linear instruction fetch for
larger instructions; sleep / trap 0xc3 re-fetches the same instruction
again.