This is the mail archive of the
gdb-patches@sources.redhat.com
mailing list for the GDB project.
[RFA] Change #3 for aix-thread.c
- From: Michael Snyder <msnyder at redhat dot com>
- To: gdb-patches at sources dot redhat dot com
- Cc: kevinb at redhat dot com, cagney at redhat dot com
- Date: Fri, 19 Jul 2002 15:42:47 -0700
- Subject: [RFA] Change #3 for aix-thread.c
- Organization: Red Hat, Inc.
Hi Kevin,
Since I already had this module and these functions loaded into
short-term memory, I went ahead and made another change, this time
to eliminate the need for ops_prepare_to_store. This patch is
really sort of an optimization, so you can take it or leave it. ;-)
It will have to be applied on top of the previous two.
Michael
2002-07-18 Michael Snyder <msnyder@redhat.com>
* (ops_prepare_to_store): Eliminate.
(init_ops): Don't initialize ops.prepare_to_store.
(store_regs_kern): Pre-fetch register buffers from child,
because some registers may not be in the cache. Copy
regs from register cache only if they are cached.
(store_regs_lib): Copy regs from register cache only
if they are cached.
(fill_sprs32, (fill_sprs64, fill_fprs, fill_gprs32,
fill_gprs64): Ditto.
Index: aix-thread.c
===================================================================
RCS file: /es/scratch/msnyder/cvsroot/aix/threads/aix-thread.c,v
retrieving revision 1.3
diff -p -r1.3 aix-thread.c
*** aix-thread.c 2002/07/18 12:07:16 1.3
--- aix-thread.c 2002/07/18 21:43:38
*************** fill_gprs64 (uint64_t *vals)
*** 1219,1225 ****
int regno;
for (regno = 0; regno < FP0_REGNUM; regno++)
! regcache_collect (regno, vals + regno);
}
static void
--- 1219,1226 ----
int regno;
for (regno = 0; regno < FP0_REGNUM; regno++)
! if (register_cached (regno))
! regcache_collect (regno, vals + regno);
}
static void
*************** fill_gprs32 (uint32_t *vals)
*** 1228,1234 ****
int regno;
for (regno = 0; regno < FP0_REGNUM; regno++)
! regcache_collect (regno, vals + regno);
}
/* Store the floating point registers into a double array. */
--- 1229,1236 ----
int regno;
for (regno = 0; regno < FP0_REGNUM; regno++)
! if (register_cached (regno))
! regcache_collect (regno, vals + regno);
}
/* Store the floating point registers into a double array. */
*************** fill_fprs (double *vals)
*** 1238,1244 ****
int regno;
for (regno = FP0_REGNUM; regno < FPLAST_REGNUM; regno++)
! regcache_collect (regno, vals + regno);
}
/* Store the special registers into the specified 64-bit and 32-bit
--- 1240,1247 ----
int regno;
for (regno = FP0_REGNUM; regno < FPLAST_REGNUM; regno++)
! if (register_cached (regno))
! regcache_collect (regno, vals + regno);
}
/* Store the special registers into the specified 64-bit and 32-bit
*************** fill_sprs64 (uint64_t *iar, uint64_t *ms
*** 1250,1261 ****
{
int regno = FIRST_UISA_SP_REGNUM;
! regcache_collect (regno, (void *) iar);
! regcache_collect (regno + 1, (void *) msr);
! regcache_collect (regno + 2, (void *) cr);
! regcache_collect (regno + 3, (void *) lr);
! regcache_collect (regno + 4, (void *) ctr);
! regcache_collect (regno + 5, (void *) xer);
}
static void
--- 1253,1270 ----
{
int regno = FIRST_UISA_SP_REGNUM;
! if (register_cached (regno))
! regcache_collect (regno, (void *) iar);
! if (register_cached (regno + 1))
! regcache_collect (regno + 1, (void *) msr);
! if (register_cached (regno + 2))
! regcache_collect (regno + 2, (void *) cr);
! if (register_cached (regno + 3))
! regcache_collect (regno + 3, (void *) lr);
! if (register_cached (regno + 4))
! regcache_collect (regno + 4, (void *) ctr);
! if (register_cached (regno + 5))
! regcache_collect (regno + 5, (void *) xer);
}
static void
*************** fill_sprs32 (uint32_t *iar, uint32_t *ms
*** 1264,1275 ****
{
int regno = FIRST_UISA_SP_REGNUM;
! regcache_collect (regno, (void *) iar);
! regcache_collect (regno + 1, (void *) msr);
! regcache_collect (regno + 2, (void *) cr);
! regcache_collect (regno + 3, (void *) lr);
! regcache_collect (regno + 4, (void *) ctr);
! regcache_collect (regno + 5, (void *) xer);
}
/* Store all registers into pthread PDTID, which doesn't have a kernel
--- 1273,1290 ----
{
int regno = FIRST_UISA_SP_REGNUM;
! if (register_cached (regno))
! regcache_collect (regno, (void *) iar);
! if (register_cached (regno + 1))
! regcache_collect (regno + 1, (void *) msr);
! if (register_cached (regno + 2))
! regcache_collect (regno + 2, (void *) cr);
! if (register_cached (regno + 3))
! regcache_collect (regno + 3, (void *) lr);
! if (register_cached (regno + 4))
! regcache_collect (regno + 4, (void *) ctr);
! if (register_cached (regno + 5))
! regcache_collect (regno + 5, (void *) xer);
}
/* Store all registers into pthread PDTID, which doesn't have a kernel
*************** store_regs_lib (pthdb_pthread_t pdtid)
*** 1301,1318 ****
/* Collect general-purpose register values from the regcache. */
for (i = 0; i < 32; i++)
! {
! if (arch64)
! {
! regcache_collect (i, (void *) &int64);
! ctx.gpr[i] = int64;
! }
! else
! {
! regcache_collect (i, (void *) &int32);
! ctx.gpr[i] = int32;
! }
! }
/* Collect floating-point register values from the regcache. */
fill_fprs (ctx.fpr);
--- 1316,1334 ----
/* Collect general-purpose register values from the regcache. */
for (i = 0; i < 32; i++)
! if (register_cached (i))
! {
! if (arch64)
! {
! regcache_collect (i, (void *) &int64);
! ctx.gpr[i] = int64;
! }
! else
! {
! regcache_collect (i, (void *) &int32);
! ctx.gpr[i] = int32;
! }
! }
/* Collect floating-point register values from the regcache. */
fill_fprs (ctx.fpr);
*************** store_regs_lib (pthdb_pthread_t pdtid)
*** 1329,1340 ****
uint32_t tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
fill_sprs32 (&tmp1, &tmp2, &tmp3, &tmp4, &tmp5, &tmp6);
! ctx.iar = tmp1;
! ctx.msr = tmp2;
! ctx.cr = tmp3;
! ctx.lr = tmp4;
! ctx.ctr = tmp5;
! ctx.xer = tmp6;
}
status = pthdb_pthread_setcontext (pd_session, pdtid, &ctx);
--- 1345,1362 ----
uint32_t tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
fill_sprs32 (&tmp1, &tmp2, &tmp3, &tmp4, &tmp5, &tmp6);
! if (register_cached (FIRST_UISA_SP_REGNUM))
! ctx.iar = tmp1;
! if (register_cached (FIRST_UISA_SP_REGNUM + 1))
! ctx.msr = tmp2;
! if (register_cached (FIRST_UISA_SP_REGNUM + 2))
! ctx.cr = tmp3;
! if (register_cached (FIRST_UISA_SP_REGNUM + 3))
! ctx.lr = tmp4;
! if (register_cached (FIRST_UISA_SP_REGNUM + 4))
! ctx.ctr = tmp5;
! if (register_cached (FIRST_UISA_SP_REGNUM + 5))
! ctx.xer = tmp6;
}
status = pthdb_pthread_setcontext (pd_session, pdtid, &ctx);
*************** store_regs_kern (int regno, pthdb_tid_t
*** 1370,1380 ****
--- 1392,1406 ----
{
if (arch64)
{
+ /* Pre-fetch: some regs may not be in the cache. */
+ ptrace64aix (PTT_READ_GPRS, tid, (unsigned long) gprs64, 0, NULL);
fill_gprs64 (gprs64);
ptrace64aix (PTT_WRITE_GPRS, tid, (unsigned long) gprs64, 0, NULL);
}
else
{
+ /* Pre-fetch: some regs may not be in the cache. */
+ ptrace32 (PTT_READ_GPRS, tid, gprs32, 0, NULL);
fill_gprs32 (gprs32);
ptrace32 (PTT_WRITE_GPRS, tid, gprs32, 0, NULL);
}
*************** store_regs_kern (int regno, pthdb_tid_t
*** 1384,1389 ****
--- 1410,1417 ----
if (regno == -1 || (regno >= FP0_REGNUM && regno <= FPLAST_REGNUM))
{
+ /* Pre-fetch: some regs may not be in the cache. */
+ ptrace32 (PTT_READ_FPRS, tid, (int *) fprs, 0, NULL);
fill_fprs (fprs);
ptrace32 (PTT_WRITE_FPRS, tid, (int *) fprs, 0, NULL);
}
*************** store_regs_kern (int regno, pthdb_tid_t
*** 1395,1401 ****
{
if (arch64)
{
! /* Must read first, not all of it's in the cache. */
ptrace64aix (PTT_READ_SPRS, tid,
(unsigned long) &sprs64, 0, NULL);
fill_sprs64 (&sprs64.pt_iar, &sprs64.pt_msr, &sprs64.pt_cr,
--- 1423,1429 ----
{
if (arch64)
{
! /* Pre-fetch: some registers won't be in the cache. */
ptrace64aix (PTT_READ_SPRS, tid,
(unsigned long) &sprs64, 0, NULL);
fill_sprs64 (&sprs64.pt_iar, &sprs64.pt_msr, &sprs64.pt_cr,
*************** store_regs_kern (int regno, pthdb_tid_t
*** 1405,1418 ****
}
else
{
! /* Must read first, not all of it's in the cache. */
ptrace32 (PTT_READ_SPRS, tid, (int *) &sprs32, 0, NULL);
fill_sprs32 (&sprs32.pt_iar, &sprs32.pt_msr, &sprs32.pt_cr,
&sprs32.pt_lr, &sprs32.pt_ctr, &sprs32.pt_xer);
if (REGISTER_RAW_SIZE (LAST_UISA_SP_REGNUM))
! regcache_collect (LAST_UISA_SP_REGNUM, &sprs32.pt_mq);
ptrace32 (PTT_WRITE_SPRS, tid, (int *) &sprs32, 0, NULL);
}
--- 1433,1447 ----
}
else
{
! /* Pre-fetch: some registers won't be in the cache. */
ptrace32 (PTT_READ_SPRS, tid, (int *) &sprs32, 0, NULL);
fill_sprs32 (&sprs32.pt_iar, &sprs32.pt_msr, &sprs32.pt_cr,
&sprs32.pt_lr, &sprs32.pt_ctr, &sprs32.pt_xer);
if (REGISTER_RAW_SIZE (LAST_UISA_SP_REGNUM))
! if (register_cached (LAST_UISA_SP_REGNUM))
! regcache_collect (LAST_UISA_SP_REGNUM, &sprs32.pt_mq);
ptrace32 (PTT_WRITE_SPRS, tid, (int *) &sprs32, 0, NULL);
}
*************** ops_store_registers (int regno)
*** 1442,1463 ****
}
}
- /* Prepare to copy the register cache to the child:
- The register cache must be fully fetched and up to date. */
-
- static void
- ops_prepare_to_store (void)
- {
- int i;
-
- if (!PD_TID (inferior_ptid))
- base_ops.to_prepare_to_store ();
- else
- for (i = 0; i < NUM_REGS; i++)
- if (!register_cached (i))
- target_fetch_registers (regnum);
- }
-
/* Transfer LEN bytes of memory from GDB address MYADDR to target
address MEMADDR if WRITE and vice versa otherwise. */
--- 1471,1476 ----
*************** init_ops (void)
*** 1602,1608 ****
ops.to_wait = ops_wait;
ops.to_fetch_registers = ops_fetch_registers;
ops.to_store_registers = ops_store_registers;
- ops.to_prepare_to_store = ops_prepare_to_store;
ops.to_xfer_memory = ops_xfer_memory;
/* No need for ops.to_create_inferior, because we activate thread
debugging when the inferior reaches pd_brk_addr. */
--- 1615,1620 ----