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[applied patch] tweak opcode fields.
- From: cgd at broadcom dot com
- To: gdb-patches at sources dot redhat dot com
- Date: 10 Feb 2002 22:13:52 -0800
- Subject: [applied patch] tweak opcode fields.
Another of my ancient patches, recycled.
The rationale for this one is, basically, if the commas delineate the
same things that the boxes do in the MIPS ISA specs, it's easier to
verify that the instructions are correct. (no need to count bits,
etc.)
verified that it compiled in the current sources; it had been tested
previously (long time ago, but the code hasn't changed 8-), and we're
using it every day in another source tree. 8-)
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
Index: mips.igen
===================================================================
RCS file: /cvs/src/src/sim/mips/mips.igen,v
retrieving revision 1.8
diff -u -r1.8 mips.igen
--- mips.igen 2002/02/11 02:19:38 1.8
+++ mips.igen 2002/02/11 06:05:20
@@ -807,7 +807,7 @@
TRACE_ALU_RESULT2 (HI, LO);
}
-000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
+000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
"ddiv r<RS>, r<RT>"
*mipsIII:
*mipsIV:
@@ -882,7 +882,7 @@
TRACE_ALU_RESULT2 (HI, LO);
}
-000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
+000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
"div r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
@@ -915,7 +915,7 @@
TRACE_ALU_RESULT2 (HI, LO);
}
-000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
+000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
"divu r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
@@ -992,7 +992,7 @@
do_dmultx (SD_, rs, rt, rd, 1);
}
-000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
+000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
"dmult r<RS>, r<RT>"
*mipsIII,mipsIV:
*vr4100:
@@ -1000,7 +1000,7 @@
do_dmult (SD_, RS, RT, 0);
}
-000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
+000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
"dmult r<RS>, r<RT>":RD == 0
"dmult r<RD>, r<RS>, r<RT>"
*vr5000:
@@ -1015,7 +1015,7 @@
do_dmultx (SD_, rs, rt, rd, 0);
}
-000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
+000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
"dmultu r<RS>, r<RT>"
*mipsIII,mipsIV:
*vr4100:
@@ -1023,7 +1023,7 @@
do_dmultu (SD_, RS, RT, 0);
}
-000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
+000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
"dmultu r<RD>, r<RS>, r<RT>":RD == 0
"dmultu r<RS>, r<RT>"
*vr5000:
@@ -1043,7 +1043,7 @@
}
-00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
+000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
"dsll r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
@@ -1054,7 +1054,7 @@
}
-00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
+000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
"dsll32 r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
@@ -1065,7 +1065,7 @@
GPR[RD] = GPR[RT] << s;
}
-000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
+000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
"dsllv r<RD>, r<RT>, r<RS>"
*mipsIII:
*mipsIV:
@@ -1081,7 +1081,7 @@
}
-00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
+000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
"dsra r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
@@ -1092,7 +1092,7 @@
}
-00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
+000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
"dsra32 r<RT>, r<RD>, <SHIFT>"
*mipsIII:
*mipsIV:
@@ -1112,7 +1112,7 @@
TRACE_ALU_RESULT (GPR[rd]);
}
-000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
+000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
"dsrav r<RT>, r<RD>, r<RS>"
*mipsIII:
*mipsIV:
@@ -1128,7 +1128,7 @@
}
-00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
+000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
"dsrl r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
@@ -1139,7 +1139,7 @@
}
-00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
+000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
"dsrl32 r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
@@ -1159,7 +1159,7 @@
-000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
+000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
"dsrlv r<RD>, r<RT>, r<RS>"
*mipsIII:
*mipsIV:
@@ -1170,7 +1170,7 @@
}
-000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
+000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
"dsub r<RD>, r<RS>, r<RT>"
*mipsIII:
*mipsIV:
@@ -1194,7 +1194,7 @@
TRACE_ALU_RESULT (GPR[rd]);
}
-000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
+000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
"dsubu r<RD>, r<RS>, r<RT>"
*mipsIII:
*mipsIV:
@@ -1233,7 +1233,7 @@
DELAY_SLOT (region | (INSTR_INDEX << 2));
}
-000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
+000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
"jalr r<RS>":RD == 31
"jalr r<RD>, r<RS>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -1247,7 +1247,7 @@
}
-000000,5.RS,000000000000000001000:SPECIAL:32::JR
+000000,5.RS,000000000000000,001000:SPECIAL:32::JR
"jr r<RS>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
@@ -1646,7 +1646,7 @@
-000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
+000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
"movn r<RD>, r<RS>, r<RT>"
*mipsIV:
*vr5000:
@@ -1657,7 +1657,7 @@
-000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
+000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
"movz r<RD>, r<RS>, r<RT>"
*mipsIV:
*vr5000:
@@ -1681,7 +1681,7 @@
-000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
+000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
"mtlo r<RS>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
@@ -1708,7 +1708,7 @@
TRACE_ALU_RESULT2 (HI, LO);
}
-000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
+000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
"mult r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
@@ -1717,7 +1717,7 @@
}
-000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
+000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
"mult r<RS>, r<RT>":RD == 0
"mult r<RD>, r<RS>, r<RT>"
*vr5000:
@@ -1741,7 +1741,7 @@
TRACE_ALU_RESULT2 (HI, LO);
}
-000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
+000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
"multu r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
@@ -1749,7 +1749,7 @@
do_multu (SD_, RS, RT, 0);
}
-000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
+000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
"multu r<RS>, r<RT>":RD == 0
"multu r<RD>, r<RS>, r<RT>"
*vr5000:
@@ -2011,7 +2011,7 @@
TRACE_ALU_RESULT (GPR[rd]);
}
-00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
+000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
"nop":RD == 0 && RT == 0 && SHIFT == 0
"sll r<RD>, r<RT>, <SHIFT>"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -2035,7 +2035,7 @@
TRACE_ALU_RESULT (GPR[rd]);
}
-000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
+000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
"sllv r<RD>, r<RT>, r<RS>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
@@ -2053,7 +2053,7 @@
TRACE_ALU_RESULT (GPR[rd]);
}
-000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
+000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
"slt r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
@@ -2108,7 +2108,7 @@
TRACE_ALU_RESULT (GPR[rd]);
}
-000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
+000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
"sltu r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
@@ -2148,7 +2148,7 @@
TRACE_ALU_RESULT (GPR[rd]);
}
-000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
+000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
"srav r<RD>, r<RT>, r<RS>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
@@ -2188,7 +2188,7 @@
TRACE_ALU_RESULT (GPR[rd]);
}
-000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
+000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
"srlv r<RD>, r<RT>, r<RS>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
@@ -2199,7 +2199,7 @@
}
-000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
+000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
"sub r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
@@ -2223,7 +2223,7 @@
TRACE_ALU_RESULT (GPR[rd]);
}
-000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
+000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
"subu r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
@@ -2346,7 +2346,7 @@
}
-000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
+000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
"sync":STYPE == 0
"sync <STYPE>"
*mipsII:
@@ -2534,7 +2534,7 @@
TRACE_ALU_RESULT (GPR[rd]);
}
-000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
+000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
"xor r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
@@ -3258,7 +3258,7 @@
// MOVF
// MOVT
-000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
+000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32::MOVtf
"mov%s<TF> r<RD>, r<RS>, <CC>"
*mipsIV:
*vr5000:
@@ -3809,14 +3809,14 @@
}
-010000,10000,000000000000000,111001:COP0:32::DI
+010000,1,0000000000000000000,111001:COP0:32::DI
"di"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
-010000,00001,5.RT,5.RD,000,0000,0000:COP0:64::DMFC0
+010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
"dmfc0 r<RT>, r<RD>"
*mipsIII,mipsIV:
{
@@ -3824,7 +3824,7 @@
}
-010000,00101,5.RT,5.RD,000,0000,0000:COP0:64::DMTC0
+010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
"dmtc0 r<RT>, r<RD>"
*mipsIII,mipsIV:
{
@@ -3832,14 +3832,14 @@
}
-010000,10000,000000000000000,111000:COP0:32::EI
+010000,1,0000000000000000000,111000:COP0:32::EI
"ei"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
-010000,10000,000000000000000,011000:COP0:32::ERET
+010000,1,0000000000000000000,011000:COP0:32::ERET
"eret"
*mipsIII:
*mipsIV:
@@ -3884,7 +3884,7 @@
}
-010000,10000,000000000000000,010000:COP0:32::RFE
+010000,1,0000000000000000000,010000:COP0:32::RFE
"rfe"
*mipsI,mipsII,mipsIII,mipsIV:
*r3900:
@@ -3906,28 +3906,28 @@
-010000,10000,000000000000000,001000:COP0:32::TLBP
+010000,1,0000000000000000000,001000:COP0:32::TLBP
"tlbp"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
-010000,10000,000000000000000,000001:COP0:32::TLBR
+010000,1,0000000000000000000,000001:COP0:32::TLBR
"tlbr"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
-010000,10000,000000000000000,000010:COP0:32::TLBWI
+010000,1,0000000000000000000,000010:COP0:32::TLBWI
"tlbwi"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
-010000,10000,000000000000000,000110:COP0:32::TLBWR
+010000,1,0000000000000000000,000110:COP0:32::TLBWR
"tlbwr"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
[24;1H[K