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Re: [RFA] mips: Fix "info registers" output
- To: Eli Zaretskii <eliz at is dot elta dot co dot il>
- Subject: Re: [RFA] mips: Fix "info registers" output
- From: Don Howard <dhoward at redhat dot com>
- Date: Thu, 21 Jun 2001 15:22:07 -0700 (PDT)
- Cc: <dmj+ at andrew dot cmu dot edu>, <gdb-patches at sources dot redhat dot com>
I submitted a patch for this problem a while ago. Here is an explaination of
the problem as I understood it:
Background: MIPS1 & 2 fp registers are 32 bits wide. To support
64bit operations, these early MIPS cpus treat fp register pairs
(f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
registers and offer a compatibility mode that emulates the MIPS2 fp
model. When operating in MIPS2 fp compat mode, later cpu's split
double precision floats into two 32-bit chunks and store them in
consecutive fp regs. To display 64-bit floats stored in this
fashion, we have to combine 32 bits from f0 and 32 bits from f1.
Throw in user-configurable endianness and you have a real mess.
I'll repost my patch shortly.
--
-Don
dhoward@redhat.com
gdb engineering