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[Patch] MIPS load_memory fix
- To: gdb-patches at sources dot redhat dot com
- Subject: [Patch] MIPS load_memory fix
- From: Ben Elliston <bje at redhat dot com>
- Date: Thu, 8 Feb 2001 10:23:26 +1100
- Cc: cagney at cygnus dot com, cgd at broadcom dot com, bje at redhat dot com
The following patch passes the current instruction address down to the
core memory accessors, for completeness. Any reason why this
shouldn't be done? Thanks,
Ben
2001-02-08 Ben Elliston <bje@redhat.com>
* sim-main.c (load_memory): Pass cia to sim_core_read* functions.
(store_memory): Likewise, pass cia to sim_core_write*.
Index: sim-main.c
===================================================================
RCS file: /cvs/src/src/sim/mips/sim-main.c,v
retrieving revision 1.1.1.2
diff -u -c -r1.1.1.2 sim-main.c
*** sim-main.c 2000/02/05 07:30:26 1.1.1.2
--- sim-main.c 2001/02/07 23:15:48
***************
*** 165,206 ****
{
case AccessLength_QUADWORD :
{
! unsigned_16 val = sim_core_read_aligned_16 (CPU, NULL_CIA, read_map, pAddr);
value1 = VH8_16 (val);
value = VL8_16 (val);
break;
}
case AccessLength_DOUBLEWORD :
! value = sim_core_read_aligned_8 (CPU, NULL_CIA,
! read_map, pAddr);
break;
case AccessLength_SEPTIBYTE :
! value = sim_core_read_misaligned_7 (CPU, NULL_CIA,
! read_map, pAddr);
break;
case AccessLength_SEXTIBYTE :
! value = sim_core_read_misaligned_6 (CPU, NULL_CIA,
! read_map, pAddr);
break;
case AccessLength_QUINTIBYTE :
! value = sim_core_read_misaligned_5 (CPU, NULL_CIA,
! read_map, pAddr);
break;
case AccessLength_WORD :
! value = sim_core_read_aligned_4 (CPU, NULL_CIA,
! read_map, pAddr);
break;
case AccessLength_TRIPLEBYTE :
! value = sim_core_read_misaligned_3 (CPU, NULL_CIA,
! read_map, pAddr);
break;
case AccessLength_HALFWORD :
! value = sim_core_read_aligned_2 (CPU, NULL_CIA,
! read_map, pAddr);
break;
case AccessLength_BYTE :
! value = sim_core_read_aligned_1 (CPU, NULL_CIA,
! read_map, pAddr);
break;
default:
abort ();
--- 165,198 ----
{
case AccessLength_QUADWORD :
{
! unsigned_16 val = sim_core_read_aligned_16 (CPU, cia, read_map, pAddr);
value1 = VH8_16 (val);
value = VL8_16 (val);
break;
}
case AccessLength_DOUBLEWORD :
! value = sim_core_read_aligned_8 (CPU, cia, read_map, pAddr);
break;
case AccessLength_SEPTIBYTE :
! value = sim_core_read_misaligned_7 (CPU, cia, read_map, pAddr);
break;
case AccessLength_SEXTIBYTE :
! value = sim_core_read_misaligned_6 (CPU, cia, read_map, pAddr);
break;
case AccessLength_QUINTIBYTE :
! value = sim_core_read_misaligned_5 (CPU, cia, read_map, pAddr);
break;
case AccessLength_WORD :
! value = sim_core_read_aligned_4 (CPU, cia, read_map, pAddr);
break;
case AccessLength_TRIPLEBYTE :
! value = sim_core_read_misaligned_3 (CPU, cia, read_map, pAddr);
break;
case AccessLength_HALFWORD :
! value = sim_core_read_aligned_2 (CPU, cia, read_map, pAddr);
break;
case AccessLength_BYTE :
! value = sim_core_read_aligned_1 (CPU, cia, read_map, pAddr);
break;
default:
abort ();
***************
*** 303,342 ****
case AccessLength_QUADWORD :
{
unsigned_16 val = U16_8 (MemElem1, MemElem);
! sim_core_write_aligned_16 (CPU, NULL_CIA, write_map, pAddr, val);
break;
}
case AccessLength_DOUBLEWORD :
! sim_core_write_aligned_8 (CPU, NULL_CIA,
! write_map, pAddr, MemElem);
break;
case AccessLength_SEPTIBYTE :
! sim_core_write_misaligned_7 (CPU, NULL_CIA,
! write_map, pAddr, MemElem);
break;
case AccessLength_SEXTIBYTE :
! sim_core_write_misaligned_6 (CPU, NULL_CIA,
! write_map, pAddr, MemElem);
break;
case AccessLength_QUINTIBYTE :
! sim_core_write_misaligned_5 (CPU, NULL_CIA,
! write_map, pAddr, MemElem);
break;
case AccessLength_WORD :
! sim_core_write_aligned_4 (CPU, NULL_CIA,
! write_map, pAddr, MemElem);
break;
case AccessLength_TRIPLEBYTE :
! sim_core_write_misaligned_3 (CPU, NULL_CIA,
! write_map, pAddr, MemElem);
break;
case AccessLength_HALFWORD :
! sim_core_write_aligned_2 (CPU, NULL_CIA,
! write_map, pAddr, MemElem);
break;
case AccessLength_BYTE :
! sim_core_write_aligned_1 (CPU, NULL_CIA,
! write_map, pAddr, MemElem);
break;
default:
abort ();
--- 295,326 ----
case AccessLength_QUADWORD :
{
unsigned_16 val = U16_8 (MemElem1, MemElem);
! sim_core_write_aligned_16 (CPU, cia, write_map, pAddr, val);
break;
}
case AccessLength_DOUBLEWORD :
! sim_core_write_aligned_8 (CPU, cia, write_map, pAddr, MemElem);
break;
case AccessLength_SEPTIBYTE :
! sim_core_write_misaligned_7 (CPU, cia, write_map, pAddr, MemElem);
break;
case AccessLength_SEXTIBYTE :
! sim_core_write_misaligned_6 (CPU, cia, write_map, pAddr, MemElem);
break;
case AccessLength_QUINTIBYTE :
! sim_core_write_misaligned_5 (CPU, cia, write_map, pAddr, MemElem);
break;
case AccessLength_WORD :
! sim_core_write_aligned_4 (CPU, cia, write_map, pAddr, MemElem);
break;
case AccessLength_TRIPLEBYTE :
! sim_core_write_misaligned_3 (CPU, cia, write_map, pAddr, MemElem);
break;
case AccessLength_HALFWORD :
! sim_core_write_aligned_2 (CPU, cia, write_map, pAddr, MemElem);
break;
case AccessLength_BYTE :
! sim_core_write_aligned_1 (CPU, cia, write_map, pAddr, MemElem);
break;
default:
abort ();