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[PATCH]: Fix 68HC11 SPI simulator
- To: gdb-patches at sourceware dot cygnus dot com
- Subject: [PATCH]: Fix 68HC11 SPI simulator
- From: Stephane Carrez <Stephane dot Carrez at worldnet dot fr>
- Date: Wed, 06 Sep 2000 00:54:57 +0200
Hi!
I've commited the following patch to fix the following problems
in the 68hc11 SPI simulator:
- SPI interrupts was not cleared
- the SPI send frame was not correct and missed the starting delay
- the sim info spi now gives better information about the current spi state.
Stephane
2000-09-06 Stephane Carrez <Stephane.Carrez@worldnet.fr>
* dv-m68hc11spi.c (m68hc11spi_io_read_buffer): Clear the interrupts.
(m68hc11spi_io_write_buffer): Likewise and fix the spi frame.
(m68hc11spi_info): Clarify the status report
of the SPI when a byte is being sent.
(m68hc11spi_clock): Fix the spi send frame.
Index: dv-m68hc11spi.c
===================================================================
RCS file: /cvs/src/src/sim/m68hc11/dv-m68hc11spi.c,v
retrieving revision 1.2
diff -p -r1.2 dv-m68hc11spi.c
*** dv-m68hc11spi.c 2000/08/11 18:44:59 1.2
--- dv-m68hc11spi.c 2000/09/05 20:47:47
*************** set_bit_port (struct hw *me, sim_cpu *cp
*** 229,236 ****
*/
! #define SPI_START_BIT 0
! #define SPI_MIDDLE_BIT 1
void
m68hc11spi_clock (struct hw *me, void *data)
--- 229,237 ----
*/
! #define SPI_START_BYTE 0
! #define SPI_START_BIT 1
! #define SPI_MIDDLE_BIT 2
void
m68hc11spi_clock (struct hw *me, void *data)
*************** m68hc11spi_clock (struct hw *me, void *d
*** 260,274 ****
controller->tx_bit--;
controller->mode = SPI_MIDDLE_BIT;
}
! else
{
controller->mode = SPI_START_BIT;
}
! /* Change the SPI clock at each event on bit 4 of port D. */
! controller->clk_pin = ~controller->clk_pin;
! set_bit_port (me, cpu, M6811_PORTD, (1 << 4), controller->clk_pin);
/* Transmit is now complete for this byte. */
if (controller->mode == SPI_START_BIT && controller->tx_bit < 0)
{
--- 261,287 ----
controller->tx_bit--;
controller->mode = SPI_MIDDLE_BIT;
}
! else if (controller->mode == SPI_MIDDLE_BIT)
{
controller->mode = SPI_START_BIT;
}
! if (controller->mode == SPI_START_BYTE)
! {
! /* Start a new SPI transfer. */
+ /* TBD: clear SS output. */
+ controller->mode = SPI_START_BIT;
+ controller->tx_bit = 7;
+ set_bit_port (me, cpu, M6811_PORTD, (1 << 4), ~controller->clk_pin);
+ }
+ else
+ {
+ /* Change the SPI clock at each event on bit 4 of port D. */
+ controller->clk_pin = ~controller->clk_pin;
+ set_bit_port (me, cpu, M6811_PORTD, (1 << 4), controller->clk_pin);
+ }
+
/* Transmit is now complete for this byte. */
if (controller->mode == SPI_START_BIT && controller->tx_bit < 0)
{
*************** m68hc11spi_info (struct hw *me)
*** 339,344 ****
--- 352,359 ----
{
signed64 t;
+ sim_io_printf (sd, " SPI has %d bits to send\n",
+ controller->tx_bit + 1);
t = hw_event_remain_time (me, controller->spi_event);
sim_io_printf (sd, " SPI operation finished in %ld cycles\n",
(long) t);
*************** m68hc11spi_io_read_buffer (struct hw *me
*** 389,394 ****
--- 404,410 ----
{
cpu->ios[M6811_SPSR] &= ~controller->rx_clear_scsr;
controller->rx_clear_scsr = 0;
+ interrupts_update_pending (&cpu->cpu_interrupts);
}
val = controller->rx_char;
break;
*************** m68hc11spi_io_write_buffer (struct hw *m
*** 466,471 ****
--- 482,494 ----
return 0;
}
+ if (controller->rx_clear_scsr)
+ {
+ cpu->ios[M6811_SPSR] &= ~controller->rx_clear_scsr;
+ controller->rx_clear_scsr = 0;
+ interrupts_update_pending (&cpu->cpu_interrupts);
+ }
+
/* If transfer is taking place, a write to SPDR
generates a collision. */
if (controller->spi_event)
*************** m68hc11spi_io_write_buffer (struct hw *m
*** 479,486 ****
/* Prepare to send a byte. */
controller->tx_char = val;
! controller->tx_bit = 7;
! controller->mode = 0;
/* Toggle clock pin internal value when CPHA is 0 so that
it will really change in the middle of a bit. */
--- 502,508 ----
/* Prepare to send a byte. */
controller->tx_char = val;
! controller->mode = SPI_START_BYTE;
/* Toggle clock pin internal value when CPHA is 0 so that
it will really change in the middle of a bit. */